Mercury High-Performance I/O Capabilities
Mercury™ devices deliver advanced I/O standards support, including CDR and source-synchronous modes for differential standards, as well as a wide variety of single-ended I/O standards (shown in Table 1).
| Table 1. I/O Standards Support |
|
I/O Standard |
Applications |
|
LVDS |
Line Side & Backplane |
|
LVPECL |
Clock Distribution |
|
PCML |
High Speed |
|
1.5-V HSTL I, II |
Cache RAMs/Fast SRAMs |
|
SSTL-3 I, II |
SDRAMs |
|
SSTL-2 I, II |
DDR SDRAMs |
|
GTL+ |
Backplane Driver |
|
3.3-V 1x/2x AGP |
Graphic Processors |
|
CTT |
JEDEC Standard |
|
3.3-V PCI |
PC, Embedded |
|
3.3-V PCI-X |
PC, Embedded |
|
3.3, 2.5, 1.8-V LVTTL |
General Purpose |
Mercury devices offer two solutions for source-synchronous differential signaling: True-LVDS™ for high-speed channels and dedicated serializer/deserializers, and Flexible-LVDS™ for a fully scalable, flexible solution.
In True-LVDS source-synchronous mode, Mercury devices can support the LVDS, LVPECL, and PCML standards at speeds of up to 840 Mbps, with a serialization/deserialization factor between 4 and 20. This capability offers numerous benefits due to the built-in dedicated circuitry. True differential I/O drivers enable high noise immunity while drastically lowering power consumption and electrical magnetic interference (EMI). Source-synchronous mode allows support for multi-drop and point-to-point backplane architecture interfaces, as well as support for data transfer across cables and connectors. This combination of source-synchronous mode and CDR mode provides a complete solution for high-speed serial communications needs. Figure 1 shows an example of how the source-synchronous mode is used to implement the RapidIO interface.
Figure 1. Implementing RapidIO in Source-Synchronous Mode
The Mercury Flexible-LVDS feature offers LVDS capability on every I/O pin for over 100 channels of LVDS support. Every I/O cell incorporates dedicated LVDS buffers to fully support advanced differential signaling.
External Memory Support
Mercury devices feature dedicated circuitry to interface with high-speed external memory, providing fast access times while improving overall system performance. Double data rate (DDR) SDRAMs double the bandwidth of traditional SDRAMs by clocking data on both rising and falling edges, as illustrated in Figure 2.
Figure 2. Double Data Rate (DDR) I/O
DDR I/O adheres to the stringent requirements of high-performance memories in servers and workstations, and serves as a vital component in empowering designers to achieve the maximum performance for next-generation systems. Mercury I/O pins have circuitry dedicated to support DDR SDRAMs at frequencies of up to 332 Mbps. Zero bus turnaround (ZBT) SRAMs eliminate data bus dead times, making them ideal for cache memory applications in network buffers and other high-bit-rate networking applications. Dedicated circuitry in Mercury devices provides I/O support on all pins at up to 200 MHz for ZBT SRAMs.
The ability to interface with advanced memories such as DDR SDRAMs and ZBT SRAMs, as well as QDR SRAMs, ensures that Mercury devices meet the demands of cutting-edge applications. Mercury devices provide an ideal solution for systems with small or large memory requirements, as seen in Figure 3. Smaller memory requirements can be addressed by the on-chip quad-port ESBs, while larger memory requirements can take advantage of the dedicated external memory interfaces.
Figure 3. The Mercury Memory Solution
PLLs & Device Clocking
Mercury devices enable extensive clock management capability through phase-locked loops (PLLs) and other advanced clocking resources. They offer up to four PLLs and 12 synthesizable clock signals per device. These 12 clock outputs can drive a variety of lines on and off of the device, increasing routing flexibility and reducing design complexity. Mercury devices provide additional dedicated clock and control-signal resources, including 4 dedicated clocks, 6 dedicated fast global signals, and 2 row-global clock signals per row. 
Based on proven circuitry and design expertise, Altera provides extended capabilities in the Mercury PLL circuitry including ClockLock™, ClockBoost™, and ClockShift™ functionality.
Flip-Chip Technology
The Mercury device family flip-chip packaging and array-driver I/O technology is a first in the programmable logic industry. In an array-driver flip-chip die, I/O pads are located in the interior section of the die, rather than on the periphery—as in a traditional wire-bond die. Flip-chip packaging improves I/O performance and reduces power consumption by greatly reducing the path length from the die to the solder ball. Additionally, flip-chip packaging enhances flexibility by providing an increased I/O count for a given die size, and improves package thermal characteristics.
Related Links
AN 131 (Using General Purpose PLLs in Mercury Devices, version 1.0, February 2001) (507kB)
Mercury Advanced CDR Support
Mercury Performance-Optimized Architecture
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