Timing Analysis Techniques
Benchmarking results can be influenced significantly depending on the interpretation of results from the different FPGA computer-aided drawing (CAD) tools. Different tools analyze circuits differently, and may lead to incorrect conclusions about the benchmarking results.
Timing Analysis Differences in Altera’s Quartus II Software & Xilinx’s ISE Software
By default, Quartus® II timing analysis makes conservative assumptions and analyzes designs to give users the most information possible. ISE trace analyzes only that which is constrained. Unconstrained paths are not reported. This means that, depending on which paths the timing analysis measures, the wrong conclusion can result.
A summary of the differences between Xilinx ISE and Altera® Quartus II software is provided in Table 1. The Performing Equivalent Timing Analysis Between the Altera Quartus II Software & Xilinx ISE white paper (PDF) contains more details.
| Table 1. Xilinx ISE Compared With Altera’s Quartus II Software: Timing Analysis Issues |
| Design Structure |
Xilinx ISE |
Altera Quartus II Software |
| Registered Clock |
- Relationship between clocks not inferred
- The output of a register can be a separate clock domain if constrained properly
|
- Relationship between clocks is inferred and the paths between them analyzed
- Can be treated as separate clock domains with constraints
|
| Gated Clock |
- Analyzed only when constrained
|
- Relationship between clocks is inferred and the paths between them analyzed
- Can be treated as separate clock domains with constraints
|
| Designs With Digital Clock Managers (DCMs) or Phase-Locked Loops (PLLs) |
- Analyzed if constraint applied to input of DCM
|
- Analyzed based on PLL clock setting made in PLL MegaWizard® Plug-In
|
| I/O Pins: Setup & Clock-to-Out Times |
- Registered clock preceding input or output register not analyzed
|
- All worst-case structures analyzed
|
| Combinational Loop |
- Not analyzed
- Warning reported
|
- Analyzed by default, but can be cut by user if desired
|
The Altera benchmark process ensures that these timing analysis differences are fixed in order to perform equivalent comparisons between Altera and Xilinx architectures.
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