The adaptive logic module (ALM) in Stratix® II devices addresses the growing usage of adder functions in FPGA designs, such as in wireless technology and digital signal processors. The Stratix II ALM contains built-in adder blocks, which can add up to three bits at a time without using any additional look-up table (LUT) resources. With this addition to the architecture, Stratix II devices offer an improvement in performance and logic utilization for general arithmetic and adder tree functions as compared to other FPGA architectures.
Figure 1 shows the Stratix II embedded adder structure. More detailed information is available in the Stratix II Device Handbook.
Figure 1. Stratix II Embedded Adder Structure
Benefits of the Stratix II Built-In Adder Circuit
The advantages of the embedded adder circuit in Stratix II devices compared to traditional 4-input LUT FPGAs include:
-
Reduction of logic utilization through packing of operand logic for adder/subtractor functions in the same ALM
-
Reduction of total logic utilization and the combinatorial logic depth for adder tree functions via the 3-bit adder
The Stratix II ALM achieves higher performance in a similar fashion—by reducing the combinatorial logic levels in the critical path and reducing routing utilization.
Full Adder
Because Stratix II devices have built-in full adders in its ALM that are separate from the LUT, the operands can be generated from the same ALM and do not require any additional logic, which is required in other FPGA architectures. Figure 2 compares the benefits of operand packing of Stratix II devices against a traditional 4-input LUT FPGA.
Figure 2. Benefit of Operand Packing for a Full Adder in Stratix II Devices
Note:
-
LE = logic element
Figure 3 shows how the following arithmetic function is implemented in different FPGA architectures.
Take the following example:
If select=0, then A op B, else A op C.
where A, B, and C are all n-bit numbers.
op can be either addition or subtraction controlled by AddSub signal
When it is implemented in a generic 4-input LUT architecture, this function will take two logic levels and six LEs. However, a Stratix II device can fit this entire design easily into one logic level in one ALM.
Figure 3. Multiplexer-before-AddSub Function Implementation Comparison
Note:
-
LAB = logic array block
Adder Tree
Another highlight to the new adder structure is the 3-input add capability. Adder trees can be found in many different applications, such as in the channel card correlator in third-generation (3G) wireless basestations. A correlator uses a large adder tree to add the filtered data samples in a given time window to recover or de-spread the data that is transmitted through spread spectrum.
Each ALM allows two bits of add operation on three different numbers. This capability can improve the performance of an adder tree significantly by collapsing the number of summation stages in the adder tree. The number of adder stages is reduced by:
Add Stage Reduction = log2 (n) – log3 (n)
where n is the count of input numbers
In addition to the reduction in the number of logic levels, the logic resource utilization is also reduced significantly because adding three 1-bit numbers only takes up half of an ALM in Stratix II devices, as opposed to two LEs in traditional 4-input LUT architectures, as shown in figure 4 .
Figure 4. Traditional 4-Input LUT vs. Stratix II 3-Input Adder Implementation
In the 128 n-bit number summation example given in Figure 5, the Stratix II logic structure reduces the logic level by 29 percent and the LE usage by almost half. The greater the number of inputs, the greater the percentage of logic level and logic resources reduction are available. To simplify the calculation, the adder output for each stage is truncated to N-bit.
Figure 5. Traditional 4-Input LUT vs. Stratix II 128 N-Bit Adder Tree Implementation Comparison (1 Bit Shown)
Adder Tree Examples
Table 1 illustrates the benefit of the Stratix II embedded adder structures.
|
Table 1. Stratix II Adder Tree Comparison With Traditional 4-Input LUT FPGAs |
|||||
|
Adder Structures |
Stratix II Devices |
Traditional 4-Input LUT FPGAs |
Notes |
||
|
Logic |
Performance |
Logic Utilization |
Performance |
||
|
36 16-bit adder |
339 ALUTs |
148 MHz |
627 LEs |
80 MHz |
Logic depth reduced from 6 to 4 |
|
128 16-bit adder |
1,209 ALUTs |
106 MHz |
2,279 LEs |
64 MHz |
Logic depth reduced from 7 to 5 |
|
128 16-bit adder pipelined |
1,462 ALUTs |
336 MHz |
2,279 LEs |
302 MHz |
Logic depth reduced from 7 to 5 |
Note :
-
ALUT = adaptive look-up table—the measure of Stratix II logic resource utilization used in Quartus® II software to represent the output of one ALM
| Table 2. Learn More about Stratix II FPGAs | |
| Topic |
Description |
| Performance Comparison | Compare Stratix II Performance with Competing Devices |
| Architecture | FPGA Architecture White Paper |
| Performance and Logic Efficiency Analysis White Paper | |
| 8-Input Fracturable LUT in the ALM | |
| Design Building Blocks | |
| DSP | DSP Blocks |
| DSP Performance Center | |
