Stratix II™ phase-locked loops (PLLs) offer innovative features such as frequency-synthesis, spread-spectrum clocking, and external feedback. Stratix II devices offer PLL reconfiguration that allows the user to change the PLL configuration without reprogramming the entire device. In addition, Stratix II PLLs offer several dynamic control features such as programmable delay shifts, programmable phase shifts, programmable bandwidth, clock power down and clock source select, and clock switchover functions.
Programmable Phase & Delay Shift
The programmable phase-shift feature allows designers to dynamically adjust the input clock phase by steps. By using this feature to manage strict timing margins, designers can meet high-speed interface requirements. The fine-tune, programmable delay shift feature provides dynamic timing delay shift control on each of the PLL outputs. Programmable delay shift lets designers meet strict I/O timing requirements by giving them the option to adjust the clock to optimize tCO or tSU.
Programmable Bandwidth
The Stratix II PLL's bandwidth is a measure of its ability to track the input clock and jitter. With Stratix™ II devices, designers can dynamically control the PLL bandwidth settings to filter out the desired amount of jitter from the input clock. A high-bandwidth PLL can quickly lock onto a reference clock and react to any changes in the clock. A low-bandwidth PLL will take longer to lock, but will filter more jitter. Stratix II’s programmable bandwidth feature offers designers greater flexibility when developing applications that require cascading PLLs.
Clock Power Down & Clock Source Select
Multiple clock input signals can be routed to the same PLL in Stratix II devices. Stratix II PLLs offer a dynamic clock source select feature that allows designers to dynamically choose between multiple clock inputs or allowing one particular clock to drive the PLL input. Each Stratix II PLL can drive up to 12 clock networks. Stratix II devices also offer a clock power-down feature that lets designers dynamically disable a particular global clock network. This feature reduces power consumption in Stratix II devices when a particular clock network is not needed in the design.
Clock Switchover
Considering the reliability requirements for today's networking systems, designers must create highly reliable systems to avoid the high costs of downtime. An effective method for creating more reliable systems is to implement redundant clocking schemes. Stratix II PLLs support a flexible clock switchover capability that allows a redundant clock to drive the PLL should the original clock fail. This clock switchover feature can also be used for switching between clock inputs of different frequencies ( e.g., clock switchover is useful for video applications that require a manual switch between operation frequencies). The clock switchover capability is widely implemented in telecommunications, storage, and server markets since these markets require highly reliable clocking schemes to insure system reliability.
Figure 1 is a block diagram of the Stratix II clock switchover circuitry.
Figure 1. Stratix II Clock Switchover Circuitry
PLL Reconfiguration
PLL reconfiguration gives designers flexibility in multiplying or dividing input clock frequencies to achieve higher or lower output clock frequencies and allows real-time variations of the PLL frequency and the output clock skew. Users can change Stratix II frequency synthesis and delay features users on-the-fly (e.g., designers can modify the PLL output frequencies and clock delays in prototype environments.) This feature allows for PLL reconfiguration without reprogramming the rest of the chip. Furthermore, during system debugging, users can change the PLL parameters to optimize the system timing.
Spread-Spectrum Clocking
To reduce electromagnetic interference (EMI) in a system, the enhanced PLLs in Stratix II devices implement spread-spectrum technology. This technology works by distributing the clock energy over a broad frequency range. Spread-spectrum clocking schemes spread the fundamental clock frequency energy to minimize energy peaks at specific frequencies. By reducing the spectrum peak amplitudes, the system will more likely meet EMI emission compliance standards and reduce costs associated with traditional EMI containment. The enhanced PLL typically provides 0.5% down-spread modulation.
Frequency Synthesis
Stratix II device's PLLs offer frequency synthesis, a capability where the input clock can be multiplied and divided to achieve a new internal clock frequency. Each Stratix II PLL supports up to six unique output clock frequencies, which allows designers to manage multiple on- and off-chip clock domains. Frequency synthesis is essential when devices must support high-speed interface standards, such as the HyperTransport™ and RapidIO™ standards, which use half-rate clocking schemes.
Frequency synthesis is achieved through counters that act as pre-divider, post-divider, and multiplier. These counters in Stratix II PLLs can be changed dynamically for enabling frequency synthesis.
External Feedback
Stratix II Enhanced PLLs can drive off-chip. The external feedback feature allows designers to adjust the off-chip clock automatically to compensate for board skew. External feedback ensures system stability by allowing the PLL to adjust the external clock output during operation to account for delay changes from temperature or voltage fluctuations. Using external feedback, designers can compensate for board delay to ensure that clock edges arrive at every external clock destination simultaneously.
