To address growing bandwidth requirements, Stratix™ GX devices feature multi-gigabit transceivers and dynamic phase alignment (DPA) circuitry for fast, reliable data transfer. Stratix GX devices are based on the same innovative core architecture as Stratix devices, with the same ground-breaking features. Outlined below are the similarities and differences between the Stratix and Stratix GX device families.
Gigabit Transceiver Blocks
Stratix GX devices feature up to 20 high-speed transceiver channels, capable of a serial data rate of up to 3.125 gigabits per second (Gbps). These channels are organized into 4-channel blocks and are optimized for 10-Gigabit Ethernet XAUI, Gigabit Ethernet, InfiniBand, Fibre Channel, SONET/SDH, SFI-5, SPI-5, PCI Express, and SMPTE 292M applications. The gigabit transceiver blocks are located on one side of the device, and replace the regular I/O banks found in Stratix devices, as shown in Figure 1. The clustered gigabit transceiver blocks facilitate channel alignment for standards requiring multiple channels. Note that Stratix and Stratix GX devices are not pin compatible.
Figure 1. Stratix & Stratix GX I/O Banks
Source-Synchronous Differential I/O Buffers
Both Stratix and Stratix GX devices feature differential I/O buffers, dedicated serialization/deserialization (SERDES) circuitry, and on-chip LVDS termination to support the LVDS, LVPECL, 3.3V PCML, and HyperTransport™ source-synchronous differential I/O standards. Stratix devices offer source-synchronous differential I/O banks on both sides of the device with a maximum data rate of 840 megabits per second (Mbps). Stratix GX devices offer source-synchronous differential I/O banks on one side of the device with a maximum data rate of 1Gbps to complement the data throughput of the transceiver channels. Stratix GX devices also feature dedicated DPA circuitry to eliminate skew and resolve signal-alignment issues, while simplifying printed circuit board (PCB) design and improving performance.
Other Features
Stratix and Stratix GX devices are built on the same 1.5-V, 0.13-µm, all-layer-copper SRAM process. This high-performance architecture features the innovative TriMatrix™ memory structure, speed-optimized digital signal processing (DSP) blocks, advanced clock-management circuitry, and on-chip termination. Table 1 summarizes the features offered by Stratix and Stratix GX devices.
| Table 1. Stratix & Stratix GX Feature Comparison | ||
| Features | Stratix | Stratix GX |
|---|---|---|
| Multi-Gigabit Transceivers | — |  |
| Source-Synchronous Differential I/Os |
|
|
| High-Performance Architecture (1) | |
|
| TriMatrix Memory (1) | |
|
| DSP Blocks (1) | |
|
| Enhanced & Fast PLLs (1), (2), (3) | |
|
| On-Chip Termination (1), (4) | |
|
| Remote System Upgrade (1) | |
|
- These features are identical in Stratix and Stratix GX devices
- PLL = phase-locked loop
- The number of enhanced and fast PLLs are not identical in Stratix and Stratix GX devices; Stratix GX devices also feature PLLs in the gigabit transceiver blocks
- Stratix GX devices also include support for termination within each transceiver channel.
The Stratix GX family offers a subset of the densities offered by the Stratix family, as shown in Table 2. For devices of equivalent densities, Stratix GX offers fewer enhanced and fast PLLs because the gigabit transceiver blocks contain internal dedicated transmitter and receiver PLLs. Stratix GX devices are offered in different package and pin-out configurations than Stratix devices, and are optimized for 3.125-Gbps operation.
| Table 2. Stratix & Stratix GX Density Comparison | ||||||||
| Stratix | Stratix GX | |||||||
|---|---|---|---|---|---|---|---|---|
| Device | LEs (1) | Source-Synchronous Channels (2) | PLLs | Device | LEs | Transceiver Channels | Source-Synchronous Channels (2) | PLLs (3) |
| EP1S10 | 10,570 | 44 | 6 | EP1SGX10C | 10,570 | 4 | 22 | 4 |
| EP1SGX10D | 10,570 | 8 | 22 | 4 | ||||
| EP1S20 | 18,460 | 66 | 6 | — | — | — | — | — |
| EP1S25 | 25,660 | 78 | 6 | EP1SGX25C | 25,660 | 4 | 39 | 4 |
| EP1SGX25D | 25,660 | 8 | 39 | 4 | ||||
| EP1SGX25F | 25,660 | 16 | 39 | 4 | ||||
| EP1S30 | 32,470 | 80 | 10 | — | — | — | — | — |
| EP1S40 | 41,250 | 90 | 12 | EP1SGX40D | 41,250 | 8 | 45 | 8 |
| EP1SGX40G | 41,250 | 20 | 45 | 8 | ||||
| EP1S60 | 57,120 | 116 | 12 | — | — | — | — | — |
| EP1S80 | 79,040 | 152 | 12 | — | — | — | — | — |
- LEs = logic elements
- The Stratix Device Family Data Sheet and the Stratix GX Device Data Sheet contain more information and details
- Enhanced and fast PLLs only are included here. Transceiver PLLs are not listed
Applications
Stratix devices are Altera's high-performance, high-density, and feature-rich FPGAs, suitable for all kinds of complex system designs. The Stratix GX family incorporates high-speed transceivers and DPA functionality, making it ideal for applications requiring fast data transfer at up to 3.125 Gbps. These applications include bridging between various high-speed protocols and implementation of switch fabrics in high-speed communications systems. Figure 2 depicts the relative differences between Stratix and Stratix GX devices in terms of I/O speed and density.
Figure 2. Stratix & Stratix GX Device I/O Speed vs. Density Comparison
