DIGILAB megAPEX High-End Prototyping System
CDC Partner: El Camino GmbH
Features
- Modular, expandable prototyping system
- Support for up to six logic modules with a total of 9 million gates (15 million system gates)
- 200-MHz system operation in a single-module setup; over 50-MHz system operation in a multi-module setup
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Logic-Module
- Choice of APEX 20KE 652-pin BGA devices, ranging from EP20K400EBC652 to EP20K1500EBC652-1X
- Optional on-chip, 32-bit RISC test engine for C/C++-based test pattern generation, pattern checking, and on-chip reference data computation
- Interface to 270 megAPEX user I/O signals to
- Feed in test pattern, using test pattern generator
- Log output signals, using logic analyzer
- 1M x 32 flash EPROM
- 1M x 32 fast SRAM
- Up to six logic modules can be cascaded
- Clock management
- Phase-locked loop (PLL) support for advanced clock generation and clock distribution
- LVCMOS and LVDS clocking options
- Two clock drivers supporting up to six logic-modules each
- Configuration management
- JTAG download cable interface
- Passive serial mode download cable interface
- EPC16 on-board configuration device
- Push button switches and user LEDs
- Power management
Termination-Module
- Access to additional I/Os
- Optional termination of GTL+ bus
Description
El Camino's DIGILAB megAPEX is a high-end modular prototyping system, based on the Altera APEX 20KE or APEX 20KC devices. Each logic module supports any Altera APEX EP20K400E, EP20K600E, EP20K1000E, or EP20K1500E device or APEX EP20K400C, EP20K600C, or EP20K1000C in a 652-pin ball-grid array (BGA) package. Up to six logic modules can be cascaded and then terminated on both ends with termination boards. The system provides a large number of inter-board connections and a high-speed common GTL+ bus. Figure 1 shows the megAPEX block diagram.
Figure 1: DIGILAB megAPEX Block Diagram 
Prototyping Concept
The DIGILAB megAPEX system uses a new and unique prototyping concept that allows engineers to implement on-chip C/C++-based test-pattern generation, pattern checking, and on-chip reference models. Each logic module ships with a Nios 32-bit RISC soft core processor, which can be optionally instantiated in a VHDL test wrapper. Within the VHDL wrapper, the RISC processor can be connected to the device under test through a flexible number of on-chip input and output ports.
Figure 2 shows the VHDL wrapper block diagram.
Figure 2. DIGILAB megAPEX VHDL Wrapper Block Diagram
The processor uses the SRAM and flash memory on each megAPEX board and can operate at up to 50 MHz, approximately equivalent to 44 MIPS. It is controlled using the RS232 interface and a basic monitor program, which run on APEX 20K embedded system block (ESB) memory. By using the monitor program together with some simple commands, it is possible to statically set and test hundreds of on-chip I/Os.
Additionally, the monitor program can be used to download complex C/C++ programs to either SRAM or flash memory (4 Mbytes each) and to start these programs. Using the RS232 interface and a standard terminal program running on a PC, it is possible to transfer debug information or to exercise menu-driven control over a test.
Figures 3 and 4 show a single-module setup and a multi-module setup with four logic modules.
Figure 3. DIGILAB megAPEX Single Module Setup
Figure 4. DIGILAB megAPEX Multi Module Setup with Four Logic Modules
Altera Devices on Board
Contact Information
For information on how to purchase this system, please contact:
El Camino GmbH
Training - Engineering - Consultancy
Landshuter Str. 1
D-84048 Mainburg
Germany
Tel. +49 (0) 8751-8787-0
Fax +49 (0) 8751-842876
E-mail: info@elca.de
WWW: http://www.elca.de/
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