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Megalogic Apex2A15 Evaluation Board

Features

  • Two high-frequency connectors, transmit and receive, containing:
    • 17 true differential pairs plus clock
    • 4 flexible differential pairs plus clock
    • 32 bi-directional LVTTL I/Os
    • Loopback board for connecting inputs and outputs on one board or for connecting 2 boards
    • Potential for custom loopback boards with additional functionality
  • Transmit and receive RJ45 connectors supporting 3 true differential pairs plus clock
  • Transmit and receive RJ45 connectors supporting 3 flexible differential pairs plus clock
  • Numerous subminiature type A (SMA) connectors containing:
    • True differential pair transmit and receive
    • Flexible differential pair transmit and receive
    • Differential clock transmit and receive
    • Differential CLKLK output and CLKLK_FB input for external control of the clock phase-locked loop (PLL)
    • High-performance "fast" input
    • Additional differential clock input
    • External clock input
  • Eight onboard true differential transmit and receive pairs
  • Mictor connector for logic analyzer
  • PMC mezzanine connector shared with 75-pin I/O on 0.1" header
  • 3 pushbutton and 4 slide switch inputs
  • RS232 I/O port
  • 10 LEDs showing board status
  • EPC16 and Joint Test Action Group (JTAG) programmability
  • Voltage regulation for single voltage input
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  Princeton Technology Group

Altera Devices on Board

  • APEX II device

Description

Princeton Technology Group, Inc is pleased to announce its APEX II evaluation board, the Megalogic Apex2A15. This board offers a rapid prototyping platform to those who are looking to evaluate high-speed components for the telecommunications industry that include the LVDS, POS-PHY Level 4, RapidIO, and HyperTransport protocols, as well as for interfacing with very high-speed analog-to-digital (A/D) and digital-to analog (D/A) convertors and other high-bandwidth transfer applications. The first board available contains an Altera® EP2A15-7 device in a 672-pin FineLine BGA package. Future boards will be available for EP2A25 and EP2A40 devices in a 672-pin FineLine BGA package. The board provides the ability to test both the True-LVDS and Flexible-LVDS differential signaling available on the APEX II device at speeds up to 1 Gbps.

Block Diagram

Figure 1 shows a block diagram of the Megalogic Apex2A15 evaluation board.

Figure 1. Block Diagram of the Megalogic Apex2A15 Evaluation Board

Figure 1. Block Diagram
Click for full detail (163KB)

Figure 2 shows the Megalogic Apex2A15 evaluation board.

Figure 2. Megalogic Apex2A15 Evaluation Board

Megalogic Apex2A15 Evaluation Board

Contact Information

For information on how to purchase this board, you can contact Princeton Technology Group at:

Princeton Technology Group
1901 N. Olden Ave. Suite 40
Ewing, NJ 08618
Telephone: (609) 434-1066
Fax: (609) 434-1067
E-mail: info@ptgroupinc.com
Web site: http://www.ptgroupinc.com

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