AMPP Partner Profile: Modelware
Overview
Modelware is a provider of silicon virtual components and design services. Since 1996, Modelware has been supplying CPLDs and ASIC functions and designs to leading telecommunications firms. Modelware's library includes an array of functions for telecommunications and data communications.
Modelware's product and service offerings span the telecommunications technology spectrum. Modelware's team has extensive industry experience through significant residencies and contributions at established telecommunications companies such as AT&T, Lucent Technologies, and its subsidiary Bell Laboratories.
Available Products
Modelware provides the AMPPSM-approved certified intellectual property (IP) cores shown in Table 1.
| Table 1. Modelware's AMPP-Approved Certified IP Cores (1) |
|
Product
|
Description
|
| Single-Channel High-Level Data Link Control (HDLC) |
The nAccess HDLC-1 Foundation core implements the HDLC protocol functions for both receive and transmit directions for a single channel. |
| Multiple-Channel HDLC |
The nAccess HDLC-4K Foundation core implements the HDLC protocol functions for both receive and transmit directions for up to 4,096 channels. |
| Inverse Multiplexing for ATM (IMA) Version 1.0/1.1 |
The IMA megafunction provides modular bandwidth, using existing physical links (for example, DS1/E1, JT2, DS3/E3), to access ATM networks and to interconnect ATM network elements. |
| ATM Adaption Layer 5 (AAL5) |
Modelware offers two modular products for AAL 5: Foundation and Manager. The AAL 5 Foundation core implements the Common Part of the AAL type 5, including the CPCS and the SAR in Streaming Mode. The AAL 5 Manager core includes the Foundation core and the memory management functions needed to support the AAL 5 Message Mode. |
| FlexBUS-3 Link Layer With FIFOs v1.0 |
The FlexBUS-3 interface allows the interconnection of physical (PHY) layer devices to Link Layer devices in 2.5 Gbps ATM and POS applications. |
| SPI-4 Phase 1 With FIFOs v1.0 (FlexBUS-4) |
The OIF SPI-4 Phase 1 core connects physical layer devices to link layer devices in
10 Gbps ATM, POS, and Ethernet applications. |
|
SPI-4.2 Foundation & Manager
|
SPI-4.2 Foundation core interfaces to the Altera® atllvds_rx and altlvds_tx blocks that perform the electrical termination and convert between the 16-bit data + 1 control bit DDR bus and 64-bit data + 4 control bits at half of the interface clock frequency.
SPI-4.2 Manager core interfaces on the user's side to multiple channels through multi-channel FIFO buffers.
|
Note:
- AMPP: Altera Megafunction Partners Program. "AMPP Approved" indicates certified IP cores that meet Altera's sales standards and have passed rigorous engineering testing.
Additional Services and Features
Modelware provides the following additional services and features:
- Single-channel TC with UTOPIA levels I/II
- Multi-channel TC with UTOPIA and µP interface
- UTOPIA levels I/II slave with first-in-first-out (FIFO) buffers
- UTOPIA levels I/II master
- UTOPIA bridge with 8/16 conversion
- UTOPIA 4 x 1 multiplexer/de-multiplexer
- UTOPIA OC12 rate cell buffer
- Resource management cell manager
- Resource management cell processor with explicit rate
- Single-channel HDLC with microprocessor interface
- Dual-channel HDLC with direct memory access (DMA) and microprocessor interface
Contact Information
For additional information, contact Modelware:
Modelware (USA)
10 West Bergen Place, Suite 105
Red Bank, NJ 07701
Tel. (732) 936-1808
Fax (732) 936-1839
Email: altera@modelware.com
URL: www.modelware.com
Modelware (Europe)
Kuechel str. 14
96047 Bamberg, Germany
Tel: +49 951 299-9870
Fax: +49 951 299-9872
Email: altera@modelware.com
URL: www.modelware.com
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