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Multi-Gigabit Fibre Channel Transport Core

from MorethanIP

View Literature
Request Free Evaluation



AMPP Approved
OpenCore Support
Atlantic(TM) Compliant



Features

  • Compliant to ANSI T11 standard specification
  • Dynamically configurable to support Gbit (1.06 Gbps Baud rate) or 2 Gbit (2.12 Gbps Baud rate) Fibre Channel applications
  • Incorporates seamless interface to commercial serializer/deserializer (SERDES) device or Fibre Channel control via standard 10-bit (Gbit operation) or 20-bit (two Gbit operation) interface
  • Configurable as N_PORT of F_PORT fabric node
  • Includes built-in client interface first-in first-out (FIFO) providing rate and clock decoupling
  • CRC-32 checks at 106.25MHz wire speed using a multi-stage CRC calculation architecture
  • Includes optional cyclic redundancy code (CRC) check and correction on the IP core transmit path, controllable on a frame-by-frame basis
  • Includes frame minimum and maximum length verification with long frame truncation and error indication
  • Implements link coding with 8B/10B providing DC balanced bitstream for efficient SERDES operation
  • Maintains 8B/10B current disparity rules with automatic correction using positive or negative encoded EOF primitives
  • Encodes negative K28.5 comma detection with automatic optical stream alignment
  • Implements FC-1 link synchronization with loss-of-synchronization indication
  • Implements Fibre Channel FC_PORT port control state machine with programmable timers
  • Provides FC Transport support for point-to-point Fibre Channel applications
  • Supports any Fibre channel traffic class and frame termination condition
  • Implements buffer-to-buffer credit management with credit recovery, credit reset and automatic R_RDY, BB_SCr and BB_SCs primitives generation
  • Includes a programmable 16-bit credit recovery timer
  • Includes a programmable transmit and receive FIFO depth
  • Available on Altera® Stratix™ GX devices with integrated SERDES providing a single-chip Fibre Channel port controller implementation
  • Includes a simple 16-Bit FIFO interface to user client application compatible with Altera Atlantic specification

Block Diagram

Figure 1. Multi-Gigabit Fibre Channel Transport Core

Figure 1. Modelware's HDLC-4K Core

Description

The core is designed to support any 1 Gbps or 2 Gbps standard Fibre Channel applications, such as point-to-point or fabric. The IP core implements the FC-1 layer functions, the FC-2 low-level functions, and, on the client side, implements a 16-Bit FIFO interface operating asynchronously from the Fibre Channel line clock. Optionally, when implemented in a Stratix GX part, the IP core implements the Fibre Channel FC-0 functions, which removes the need to use an external SERDES device.

The FC-2 layer provides services such as CRC generation and check, Fibre Channel compliant frames generation, frame encapsulation, buffer-to-buffer credit with the necessary Fibre Channel timers, and link set-up FC_PORT state machines. The FC-1 function implements line coding (8B/10B), maintains DC balancing on the line, Fibre Channel primitive sequences generation and decoding, receive data alignment and link synchronization. On the line interface, the IP core implements a standard programmable 10-bit/20-bit interface that can be connected to any Gigabit/2 Gigabit commercial, or embedded (with Altera Stratix GX devices) SERDES.

The IP core implements statistic event counters and a generic 32-bit host interface, providing advanced network management and configuration functions.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Target Device Speed Grade Logic Elements (LEs) Performance
(fMAX)
Parameter Setting
EP1S10 -7 4000 115 MHz 106.25 MHz
EP1SGX10 -7 4000 115 MHz 106.25 MHz
EP1C6 -7 3000 118 MHz 106.25 MHz

Deliverables

  • Register Transfer Level (RTL) synthesizable VHDL/Verilog source code or encrypted net list
  • Configurable VHDL/Verilog verification test-benches
  • Scripts for Mentor Graphics LeonardoSpectrum™ synthesis tool
  • Scripts for Synplicity, and Synplify synthesis tools
  • Implementation script for Quartus® II V3.0
  • Detailed user's guide and reference guide

Contact Information:

For additional information, contact:

MorethanIP
An der Steinernen Bruecke 1
D-85757
Karlsfeld Germany

Tel: +49 81-31-333-9390 (Germany) or +1 408 273 4567 (USA)
Fax: +49 81-31-333-9391 (Germany) or +1 408 273 4667 (USA)
E-mail: info@morethanip.com
URL: www.morethanip.com

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