FlexBUS-3 Link Layer with FIFOs V1.0
Features
- AMCC-compatible FlexBUS-3 link layer with FIFO buffers
- Asynchronous transfer mode (ATM) and packet over SONET (POS) modes
- Single- and multi-link operation, scalable from 1 to 48 links
- Programmable per-port bandwidth allocation
- Direct and polled cell/packet available modes
- Programmable FIFO size with programmable almost empty/almost full thresholds
- Programmable burst size
- Automatic link selection based on FIFO fill levels and cell/packet available information
- 32-bit data bus width
- Parity generation and checking
- Altera® Atlantic™ interface (slave) on user's side
- Full synchronous design which exceeds Clk = 104 MHz
- Fully automatic test bench including driver and monitor
- Easy to use in multiplexer/demultiplexer and bridge functions
Block Diagram
Figure 1 shows the block diagram for the FlexBUS-3 core.
Figure 1. Block Diagram
Description
The FlexBUS-3 interface allows the interconnection of physical (PHY) layer devices to Link Layer devices in 2.5 Gbps ATM and POS applications. Modelware's FlexBUS-3 Link Layer core performs the interface functions on the Link Layer side of the interface.
The core interfaces to the Link Layer via Altera's Atlantic interface, and to the Physical Layer via the FlexBUS-3 interface (Figure 1). The Flex3 Transmitter block monitors the Transmitter FIFO fill levels and the Transmitter cell/packet available information received from the PHY Layer device. If a Transmitter FIFO has data and the cell/packet available information for the corresponding channel indicates that it is ready to accept data, the Flex3 Transmitter block initiates a data transfer from the Transmitter FIFO to the PHY device.
The Flex3 Receiver block monitors the Receiver FIFO buffers fill levels and the Receiver cell/packet available information from the PHY device. If a Receiver FIFO can accept a cell or packet burst and the cell/packet available information for the corresponding channel indicates that it is ready to send data, the Flex3 Receiver block initiates a data transfer from the PHY device to the Receiver FIFO.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| APEXTM 20KE |
-1 |
3,250 |
24 |
28 MHz |
4 Channels |
| APEX 20KE |
-1 |
14,000 |
100 |
104 MHz |
16 Channels |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Modelware:
Modelware (USA)
10 West Bergen Place
Suite 105
Red Bank, NJ 07701
Tel. (732) 936-1808
Fax (732) 936-1839
E-mail: altera@modelware.com
URL: www.modelware.com
Modelware (Europe)
Kuechel str. 14
96047 Bamberg, Germany
Tel: +49 951 299-9870
Fax: +49 951 299-9872
Email: altera@modelware.com
URL: www.modelware.com
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