SPI-4 Phase 1 with FIFOs v1.0 (FlexBUS-4)
Features
- Optical Interworking Forum's (OIF) compliant SPI-4 phase 1 (compatible with AMCC FlexBUS-4) with FIFO buffers
- ATM, packet over SONET (POS), and direct data mapping modes
- Single- and multi-link operation, scalable from 1 to 16 links
- Programmable per-port bandwidth allocation
- Programmable FIFO size with programmable almost empty/almost full thresholds
- Programmable burst size
- Automatic link selection in the source block based on the source FIFO threshold and flow control information
- 64-bit data bus width
- Parity generation/checking over data and control words
- Supports the Altera® AtlanticTM Interface on the user side
- Fully synchronous design, exceeds 200 MHz
- Fully automatic testbench, including driver/monitor
- Easy to use in multiplexer/demultiplexer and bridge functions
Block Diagram
Figure 1 shows the block diagram for the SPI-4 Phase 1 with FIFO buffer core.
Figure 1. Block Diagram
Description
The OIF SPI-4 Phase 1 core connects physical layer devices to link layer devices in 10-Gbps ATM, POS, and Ethernet applications. Modelware's SPI-4 Phase 1 core performs the interface functions on both sides of the interface. On the system side, the SPI-4 Phase 1 core connects to a single link or to multiple links or ports via Altera's Atlantic interface.
The Spi4Tx block monitors the source FIFO buffer's fill level and the flow control information received from the opposite side of the SPI-4 interface. If a source FIFO buffer has data and the flow control information for the corresponding channel indicates that it is ready to accept data, the Spi4Tx block initiates a data transfer from the source FIFO buffer towards the SPI-4 interface.
The Spi4Rx block transmits the sink FIFO status information to the opposite side according to the sink FIFO almost-full flags. The Spi4Rx block stores data received for a particular link in that link's FIFO buffer. The Sink FIFO flags indicate to the user the presence of data in the FIFO buffer(s).
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| APEXTM II |
-1 |
2,700 |
23 |
200 MHz |
Contact Modelware |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Modelware:
Modelware (USA)
10 West Bergen Place
Suite 105
Red Bank, NJ 07701
Tel. (732) 936-1808
Fax (732) 936-1839
E-mail: altera@modelware.com
URL: www.modelware.com
Modelware (Europe)
Kuechel str. 14
96047 Bamberg, Germany
Tel: +49 951 299-9870
Fax: +49 951 299-9872
Email: altera@modelware.com
URL: www.modelware.com
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