from Altera
     |
Features
- Configurable datapath width (32 bits, 64 bits, 128 bits)
- Supports up to 256 ports
- POS-PHY Level 4 MegaCore® function throughput rate:
- From 840 Mbps to 1,250 Mbps per LVDS lane for Stratix® series FPGAs and HardCopy® series ASICs
- Up to 840 Mbps per LVDS lane for Arria® GX series FPGAs
- From 250 Mbps per LVDS lane (32-bit system datapath) to 622 Mbps (64-bit system datapath) for Cyclone® series FPGAs
- Fixed start of packet (SOP) alignment to the most significant byte lane eases subsequent packet processing
- FIFO buffer status management and indications
- Run-time programmable calendar length, burst size, and threshold levels
- Asymmetric ports and hitless bandwidth re-provisioning
- Error detection and handling
- Easy-to-use intellectual property (IP) toolbench interface and functional simulation models in Verilog and VHDL
Industry Standards Compliant
- Optical Internetworking Forum, System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices, OIF-SPI4-02.0, January 2001
- PMC-Sierra Inc., POS-PHY Level 4 A Saturn Packet and Cell Interface Specification for OC-192 SONET/SDH and 10-Gbps Ethernet Applications, Issue 5 (Draft), June 2000
General Description
The packet over SONET/SDH PHY (POS-PHY) Level 4 interface, first developed by the SATURN Development Group, was later adopted by the Optical Internetworking Forum (OIF) as the System Packet Interface Level 4—Phase 2 (SPI-4.2). Therefore, POS-PHY Level 4 and SPI-4.2 are synonymous.
The POS-PHY Level 4 MegaCore function uses the SPI-4.2 interface for high-speed cell and packet transfers between PHY and link-layer devices. The SPI-4.2 interface supports a data width of 16 bits (LVDS solution), and can be a PHY-link, link-link, link-PHY, or PHY-PHY connection in multi-gigabit applications, including ATM and POS (STS-192/STM-64), 10 Gigabit Ethernet, and multi-channel gigabit and fast Ethernet.
Applications
- 10- to 20-Gbps POS or packet over Asynchronous Transfer Mode (ATM) interface in Internet protocol switch/routers, WAN switches, SONET cross connects, or multiplexers
- Interconnect for network processing unit (NPU) to Ethernet media access control (MAC), SONET framer to Ethernet MAC, or ATM link layer to PHY devices
- Bridge or aggregation for POS-PHY to POS-PHY, or Ethernet MAC to MAC
Figure 1 shows typical applications of the POS-PHY Level 4 MegaCore function.
Figure 1. POS-PHY Level 4 MegaCore Function Configured for the Link Layer
Figure 2. POS-PHY Level 4 MegaCore Function Configured for PHY
OpenCore Plus Evaluation
Use the Altera® OpenCore Plus Evaluation flow to test drive this IP core.
Performance
Typical expected performance and utilization figures for this core function are provided in the POS-PHY Level 4 MegaCore User Guide (PDF).
I-Tested
Altera awards the I-Tested certification to MegaCore functions or Altera Megafunction Partners Program (AMPPSM) IP cores that have been verified in an Altera FPGA on an evaluation board with ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.
The POS-PHY Level 4 MegaCore function is interoperable with various ASSP vendor devices. Contact your local Altera sales representative or field applications engineer (FAE) for more information.
Technical Support
For technical support on the POS-PHY Level 4 MegaCore Function, please visit the POS-PHY Level 4 MegaCore Support Center. Additional support for MegaCore functions is available in the Altera mySupport online issue tracking system.
