Altera and its third-party intellectual property (IP) partners offer a large selection of off-the-shelf megafunctions optimized for Altera® devices. All Altera IP cores are rigorously tested and optimized for the highest performance and lowest cost in Altera's programmable logic devices (PLDs). You can implement these parameterized blocks of IP easily, reducing design and test time.
Time-to-Market
Use of IP cores reduces time-to-market because you can avoid the process of designing standardized functions from scratch. Altera and partner IP enable you to concentrate on higher-level design elements and to focus on product improvement and differentiation.
Core Evaluation and Licensing
Altera’s OpenCore Plus evaluation feature allows you to simulate the behavior of an Altera IP core within the targeted system, verify the functionality of the design, and evaluate its size and speed quickly and easily. In addition, the Quartus® II software generates time-limited programming files for designs containing Altera IP, allowing device programming and design verification before license purchase.
For more information about core download, evaluation and licensing, visit Altera's Getting Started page.
IP Toolbench for Core Parameterization
Altera IP cores are fully parameterizable through IP Toolbench. IP Toolbench is a toolbar from which you can quickly and easily view documentation, specify parameters, set up third-party tools, and generate all the files necessary for integrating the parameterized MegaCore® function into a design. You can launch IP Toolbench from within the Quartus II software. See Figure 1.
Figure 1. IP Toolbench
Altera's MegaWizard® Plug-In Manager, launched from IP Toolbench, allows core customization to exact system requirements through an intuitive GUI. An example MegaWizard plug-in is shown in Figure 2.
Figure 2. MegaWizard Plug-In
Simulation
IP Toolbench generates IP functional simulation models for any parameterized MegaCore variant. An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model file produced by the Quartus II software version 3.0 or higher. The models allow for fast functional simulation of IP using industry-standard VHDL or Verilog HDL simulators.
For post-place-and-route simulation, the Quartus II software provides a flexible simulation environment through a native simulator within the Quartus II software or through VHDL and Verilog output netlists.
Synthesis and Compilation
To ensure consistent best-in-class performance and facilitate drop-in instantiation of cores, IP Toolbench automatically generates optimized code ready for compilation through the Quartus II development software.
Development Kits
Altera and its partners offer a wide variety of development kits that are the ideal platforms to develop and test designs containing IP cores. Altera’s OpenCore Plus hardware evaluation and development kit makes a powerful combination that translates to the fastest possible time-to-market. The development kits page contains a complete list of Altera and partner development kits.
