Digital PLL Synthesizer
Features
- General-purpose digital frequency phase synthesizer
- Used to synchronize a data stream to a reference
- Synthesizes an output clock and precise phase from a high-speed clock input. Both outputs are phase-locked to the reference input.
- Provides lock indicator output
- Includes parameterized loop bandwidths, damping factor, lock threshold
- Separate loop parameters for before and after lock greatly reduces jitter
- Output frequency can be changed on-the-fly
- Designed for maximum speed (fMAX > 170 to 330 MHz, depending on device family)
- Optimized for ACEX™ 1K, FLEX® 10KE, APEX™ 20KE, APEX 20KC, and Mercury™ devices
- Ideal for the following applications:
- Digital tuners
- Digital modulators
- Digital demodulators
- Wireless & wired telecommunications systems
Block Diagram
Figure 1 shows the block diagram for the megafunction.
Description
CommStack's Digital PLL Synthesizer megafunction generates a clock signal dclk and precise phase information that is phase-locked to the reference input, at a rational multiple N/M, provided that F(clk) >> 2 * F(ref) * N/M. The dclk signal may be used to clock circuitry running at a multiple of the symbol rate, and the phase information, updated at the F(clk) rate, may be a critical input to an interpolator which outputs samples at the same [F(clk)] rate.
The nominal output frequency may be set at any time as a fraction of F(clk) by placing this fractional value on F0[27..8], placing M on Lim[7..0], and resetting the circuit. Loop gains are set as compile-time parameters. Both pre-lock and post-lock gains may be set separately, as well as the lock indicator gain itself. A MATLAB support program is provided to assist in determining these gains as a function of F(ref), F(dclk), F(clk), and the desired loop bandwidths and damping factors.
This function may be utilized for symbol clock and phase generation in digital modulator and demodulator designs (i.e., Data-over-Cable Service Interface Specification (DOCSIS), LMDS, or MMDS applications.)
With performance from 170 MHz to over 330 MHz, the CommStack Digital PLL Synthesizer megafunction provides a high-speed and flexible frequency and phase synthesis capability well suited to many modern digital signal processing (DSP) applications.
Device Utilization Examples
Table 1 lists the typical device utilization results for the megafunction.
| Table 1: Typical Device Utilization for Megafunction |
| Device |
Speed Grade |
Logic Cells |
EABs (1) |
fMAX (typical) |
EP1K100,
EPF10K100E |
-1 |
344 |
0 |
175 MHz |
| EP20K100E |
-1 |
407 |
0 |
170 MHz |
| EP20K100C |
-7 |
407 |
0 |
210 MHz |
| EP1M120 |
-5 |
373 |
0 |
333 MHz |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact
CommStack, Inc.
72 Fairfax Avenue
Atherton, CA 94027
Phone: (650) 701-0939
E-mail: info@commstack.com
Internet: http://www.commstack.com
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