from Microtronix Inc.
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Features
- 7:1 serializer/deserializer (SERDES)
- Optimized for 8- and 10-bit HD video applications
- Supports both 28-bit and 35-bit parallel data (mapped into 4/5 LVDS channels)
- Supports flat panel resolutions up to 1080p at 120 Hz and higher
- Cascade cores to support wider LVDS links (dual at quad, etc.)
- LVDS TxClock aligned to data, no phase-locked loop (PLL) fine tuning required
- Receiver auto aligns clock to encoded video data from input LVDS data stream
- Configuration GUI streamlines design process
- Complies with Open LDI specification for digital display Interfaces
- Supports Cyclone® II and Cyclone III FPGAs
Block Diagram
Figure 1. The Microtronix Video LVDS SERDES Transmitter/Receiver Intellectual Property (IP) Core
Description
The Microtronix Video LVDS SERDES transmitter/receiver IP core provides a complete, easy-to-use SERDES solution to interface a wide variety of video host systems to flat panel displays. This core is specifically targeted at high-performance video applications including flat panel displays, HDTV consumer electronics, video display resolution conversion/enhancement equipment, automotive navigation/DVD entertainment systems, and high-speed interconnects.
The transmitter and receiver cores support both 28-bit (8-bit RGB) and 35-bit (10-bit RGB) parallel data configurations using either 4 or 5 LVDS serial channels. You can cascade transmitter and receiver cores to create dual and quad LVDS links supporting display panel resolutions up to 1080p at 120 Hz and higher. A phase-locked transmit clock is generated synchronous to the video data. It is transmitted in parallel with the data streams over a separate LVDS link. The IP core runs at the maximum LVDS data rates of the Altera Cyclone II and Cyclone III FPGAs.
You can use the core to support Open LDI or VESA or other video specifications for the encoding of data for digital display interfaces by custom mapping the input data to the encoded LVDS data bits.
Deliverables
The Video LVDS SERDES Transmitter/Receiver IP core package includes:
- Encrypted source code
- ModelSim®/VHDL pre-compiled simulation library
- Reference designs for Altera® and Microtronix development kits
- Single or multi-user licensing
- Technical support
Contact Information
For additional information, contact Microtronix Datacom Ltd. at:
Microtronix
9-1510 Woodcock Street
London, ON, Canada N6H 5S1
Tel: +1 (519) 690-0091
Fax: +1 (519) 690-0092
Email: sales@microtronix.com
URL: www.microtronix.com
