DFPMUL Floating-Point Pipelined Multiplier Unit
Features
- Fully complies with the IEEE 754 specification
- Single-precision real format support
- Simple interface
- No programming required
- Seven levels of pipelining
- Full accuracy and precision
- Overflow, underflow, and invalid operation flags
- Results available at every clock
- Fully configurable
- Fully synthesizable, static synchronous design with no internal tri-states
Description
The DFPMUL floating-point pipelined multiplier unit function uses the pipelined mathematics algorithm to multiply two arguments. The input number format complies with the IEEE 754 specification, and the function supports single-precision real numbers. The multiply operation can be pipelined up to 7 levels. The input data are fed in every clock cycle. The latency before the first result appears depends on the level of pipelining; subsequent results are available at each clock cycle. The DFPMUL megafunction offers full accuracy and precision.
Block Diagram
Figure 1 shows the block diagram for the DFPMUL megafunction.
Figure 1. Block Diagram
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Parameter Setting |
| Logic Cells |
Performance
(fMAX) |
| FLEX® EPF10K30E |
-1 |
2609 |
33 MHz |
Contact Digital Core Design |
| APEXTM EP20K100E |
-1 |
2632 |
40 MHz |
Contact Digital Core Design |
| ACEX® EP1K100E |
-1 |
2617 |
38 MHz |
Contact Digital Core Design |
Contact Information
For additional information, contact Digital Core Design at:
Digital Core Design
Wroclawska 94
41-902 Bytom, Poland
Tel. +48 32 282 82 66
Fax +48 32 282 74 37
E-mail: info@dcd.com.pl
URL: www.dcd.com.pl
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