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主页 > 产品 > IP > DSP > Arithmetic > DFPAU - Floating Point Arithmetic Unit 打印此页 发送此页 DFPAU - Floating Point Arithmetic Unit from Digital Core Design Features Direct replacement for C float software functions such as: +, -, *, /,==, !=,<=, <=, <,> C interface supplied for Altera® Nios® embedded processors, 8051 compilers No programming required Single precision real format support-float type Flexible arguments and result registers location Performs the following functions: FADD, FSUB—addition, subtraction FMUL, FDIV—multiplication, division FSQRT—square root FCHS, FABS—change of sing, absolute value FXAM—examine input data FUCOM—comparison Exceptions built-in routines Masks each exception indicator Precision lack PE Underflow result UE Overflow result OE Invalid operand IE Division by zero ZE Denormal operand DE Fully synthesizable, static synchronous design with no internal tri-states Optimized for use with the Nios embedded processors Block Diagram Figure 1 shows a block diagram of the function. Figure 1. DFPAU - Floating Point Arithmetic Unit View full detail (55 KB) Description DFPAU uses the specialized algorithms to compute arithmetic functions. It supports addition, subtraction, multiplication, division, square root, comparison, absolute value, and change sign of a number. DFPAU supports single precision real numbers of IEEE-754 standard. DFPAU is well-suited for use with the 32-bit Nios processor. Device Utilization Example Table 1 lists the typical device utilization results for the megafunction. Table 1. Typical Device Utilization for the Megafunction Device Speed Grade Utilization Parameter Setting Logic Elements Performance (fMAX) Stratix® -7 2627 64 MHz Contact Digital Core Design APEX™ 20KE -1 2668 40 MHz Contact Digital Core Design APEX 20KC -7 2654 48 MHz Contact Digital Core Design APEX II -7 2670 54 MHz Contact Digital Core Design Deliverables Hardware description language (HDL) source code package includes: VHDL or Verilog source code VHDL or Verilog test bench environment Active-HDL automatic simulation macros ModelSim® automatic simulation macros Full tests with reference responses Synthesis scripts Encrypted megafunction package includes: EDIF or Text Design File (.tdf) netlist optimized for particular technology Core instantiation inside Quartus® II or MAX+PLUS® II environments Symbol, include, assigments, and configuration files Compilation, simulation, and programming ready project Each package includes: Technical documentation Installation notes HDL core specification Data sheet Example application Technical support Intellectual property (IP) core implementation support Three months of maintenance, including phone and e-mail support Contact Information For additional information, contact DIgital Core Design at: Wroclawska 94 41-902 Bytom, Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: info@dcd.pl URL:  www.dcd.com.pl 给本页评分

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