X_DES Cryptoprocessor
Features
- Fully compliant 56-bit data encryption standard (DES) implementation
- Supports encryption and decryption
- Encryption and decryption performed in 16 clock cycles
- No dead cycles for key loading or mode switching
- Suitable for triple DES implementations
- Suitable for electronic code block (ECB), cypher block coding (CBC), cypher feedback (CFB), and output feedback (OFB) implementations
- Sustained bit rate is 4x clock speed
- High clock speed and low gate count achieved
- Fully synchronous design
- Available as fully functional and synthesizable VHDL or Verilog HDL source code
- Test benches provided
Block Diagram
Figure 1 shows the block diagram for the X_DES megafunction.
| Figure 1. Block Diagram |
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Description
The X_DES megafunction is a fully compliant hardware implementation of the DES encryption algorithm, suitable for a variety of applications. The DES is a block cipher that encrypts and decrypts data in 64-bit blocks using a 56-bit key.
After an initial permutation, the megafunction splits the input data into two 32-bit words, and directs the results left and right in 16 identical operation cycles.
The right word is processed with an expansion permutation, XORed with the processed key, and substituted using S boxes. The output of the S boxes is permuted and then XORed with the left word. At the end of each round, the resulting data updates the right word register, and the initial right word is stored in the left word register. The shift and permutation operations allow the processed key to change in every round.
After the last operation is completed, the left and right words are reassembled and passed through the inverse of the initial permutation. The X_DES megafunction determines whether to encrypt or decrypt by reading the level of the E_D signal input port. A rising input on the GO port triggers a cryptographic operation on the DIN signal using the KEY signal as the key. The DES algorithm allows only 56 of the 64 bits of the KEY input port to be read by the megafunction. One bit out of every eight bits is ignored from the KEY input, and after 16 clock cycles, the READY output indicates that the DOUT signal value is valid.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Target Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter
Setting |
| LEs (1) |
ESBs (2) |
| EPF6016 |
-2 |
540 |
- |
37 MHz |
Contact CAST |
| EPF81500 |
-2 |
540 |
- |
44 MHz |
Contact CAST |
| EPF10K20 |
-3 |
540 |
- |
35 MHz |
Contact CAST |
| EPF10K30A |
-1 |
570 |
- |
73 MHz |
Contact CAST |
NotesTable 1 lists the typical device utilization results for the megafunction.
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- EABs = Embedded array blocks
Contact Information
For additional information, you can contact CAST, Inc. at:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677, USA
Phone: +1 (845) 353-6160
Fax: +1 (845) 727-7607
E-mail: OpenCore@cast-inc.com
URL: www.cast-inc.com
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