Turbo Encoder MegaCore Function
from Altera Corporation
SUPPLY OF THIS IP CORE DOES NOT CONVEY A LICENSE NOR IMPLY ANY RIGHT TO USE ANY TURBO CODES PATENTS OWNED BY FRANCE TELECOM, TDF OR GET. PLEASE CONTACT FRANCE TELECOM FOR INFORMATION ABOUT TURBO CODES LICENSING PROGRAM AT THE FOLLOWING ADDRESS:
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New in Version 1.6.0
- Support for Cyclone™ II devices
Features
- Compliant with the 3rd Generation Partnership Project (3GPP); Technical Specification Group Radio Access Network; Multiplexing and Channel Coding (FDD) (3G TS 25.212 version 3.2.0)
- Supports selectable double buffering of data
- Supports parallel outputs
- Supports high-speed downlink packet access (HSDPA) data rates
- Dramatically shortens design cycles
- Easy-to-use IP Toolbench interface
- IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
- Support for OpenCore® Plus evaluation
- Support for Stratix® II, Stratix GX, Stratix, Cyclone II, Cyclone, Mercury™, Excalibur™, HardCopy®, APEX™ II, APEX 20KE, APEX 20KC, and APEX 20K device families
General Description
A significant amount of research has been done to make efficient use of available bandwidth. This research has led to the development of sophisticated coding schemes. The product of this research was the creation of the Viterbi and Reed-Solomon decoders. Since then, a new method has emerged. A combination of iteratively run soft in/soft out decoders with simple component codes and an interleaver futher narrows the gap to the theoretical limit (Shannon limit). This process is referred to as turbo coding or iterative decoding.
The block diagram of a turbo encoder/decoder is shown in Figure 1.
Figure 1. Turbo Encoder/Decoder Block Diagram
 Click for full detail (99 KB)
The Turbo Encoder
The turbo encoder MegaCore® function uses a stream-driven implementation and feeds the incoming information bits through to the output. In addition, it encodes them using encoder 1, a recursive convolutional encoder. It also feeds the information bits via a pseudo random interleaver into encoder 2. The encoded bit streams can be punctured to save bandwidth.
Interleavers
Interleaving is the process of reordering a binary sequence in a systematic way. Convolutional codes are designed to combat random independent errors. However, errors typically come in bursts rather than being randomly distributed. Interleaving can be used to disperse the burst errors, making them easier to correct.
The turbo encoder interleaver, as defined by 3GPP, is a third-stage interleaver with a block size between 40 and 5,114 bits. The input sequence is first written row by row into a matrix. The rows are then algebraically interleaved, based on sets of prime integers. Each row is then interleaved with a predefined pattern. The output sequence is generated by reading out the matrix, column by column. The output sequence is altered in the cases where the input sequence does not exactly fill the matrix.
OpenCore Plus Evaluation
With Altera's free OpenCore Plus evaluation feature, you can perform the following actions:
- Simulate the behavior of a MegaCore function within your system
- Verify the functionality of your design, as well as evaluate its size and speed quickly and easily
- Generate time-limited device programming files for designs that include MegaCore functions
- Program a device and verify your design in hardware
You only need to purchase a license for the MegaCore function when you are completely satisfied with its functionality and performance, and want to take your design to production.
Performance
Table 1 shows the typical performance using the Quartus® II version 4.0 software available in Stratix II, Stratix, and Cyclone devices.
| Table 1. Performance |
|
Device |
Logic Elements (LEs)) |
Memory (Bits) |
fMAX (MHz) |
| Stratix II (1), (2) |
1,669 |
17,152 |
157 |
| Stratix (3) |
2,057 |
17,152 |
101 |
| Cyclone (4) |
2,057 |
17,152 |
101 |
Notes:
- EP2S15F484C3 device.
- The Quartus II software reports the number of adaptive look-up tables (ALUTs) that the design uses in Stratix II devices. The LE count is based on this number of ALUTs.
- EP1S10F484C5 device.
- EP1C3T100C6 device.
Technical Support
For technical support on this MegaCore function, please visit the Altera mySupport on-line issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.
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