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Viterbi Compiler

from Altera Corporation

View Literature
Download Free Evaluation



OpenCore Plus Support
DSP Builder Ready
Atlantic(TM) Compliant



New in Version 7.0

  • Preliminary support for Cyclone® III devices

Features

  • High-performance, area-optimized, soft-decision Viterbi decoders for error correction
  • High-speed parallel architecture with:
    • Performance of over 240 megabits per second (Mbps)
    • Fully parallel operation
  • Low- to medium-speed, hybrid architecture
    • Configurable number of add compare and select (ACS) units
    • Memory-based architecture
    • Wide range of performance; wide range of logic area
  • Fully parameterized Viterbi decoder, including:
    • Number of coded bits
    • Constraint length
    • Number of soft bits
    • Traceback length
    • Polynomial for each coded bit
  • Avalon® Streaming interfaces
  • Variable constraint length
  • Trellis coded modulation (TCM) option
  • Enhanced block decoding
  • Easy-to-use IP Toolbench interface
  • DSP Builder ready
  • VHDL testbenches to verify the decoder
  • IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
  • Flexible licensing—use only the features you require
  • Support for Stratix® III, Stratix II, Stratix II GX, Stratix GX, Stratix, Cyclone III, Cyclone II, Cyclone, HardCopy® II, and HardCopy Stratix device families

General Description

The Altera Viterbi Compiler comprises high-performance, soft-decision Viterbi MegaCore® functions that implement a wide range of standard Viterbi decoders.

Viterbi decoding (also known as maximum likelihood decoding or forward dynamic programming) is the most common way of decoding convolutional codes by using an asymptotically optimum decoding technique. In its basic form, Viterbi decoding is an efficient, recursive algorithm that performs an optimal exhaustive search.

A convolutional encoder and Viterbi decoder are typically used together to provide error correction over a noisy channel, e.g., a communications channel.

IP Evaluation

Use Altera’s free OpenCore Plus Evaluation feature to test drive this MegaCore function.

Performance & Resource Utilization

Typical expected performance and utilization figures for this MegaCore function are provided in the User Guide.

Technical Support

For technical support on this MegaCore function, please visit the Altera mySupport on-line issue tracking system.

Related Documents

For more information on the Viterbi Compiler, refer to the following documents:

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