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Reed-Solomon Encoder

from Amphion Semiconductor, Ltd.

Request Free Evaluation



AMPP Approved
OpenCore Support



Features

  • Configurable solution for high data rate Reed-Solomon encoding
  • Supports a range of standards, including European Telecommunication Standards (ETS) 300-421 and ETS 300-429.
  • Single implementation supports any valid block length
  • Processes both burst and continuous data
  • Supports high-speed applications (up to 400 Mbps)
  • Symbol wide input and output, clocked by single symbol rate clock (higher rate clocks, if available, can be used to reduce gate count)
  • Low latency implementation: two symbol clock cycles
  • Simple function interface allows easy integration into larger systems

Block Diagram

Figure 1 shows the block diagram for the Reed-Solomon encoder megafunction.

Figure 1. Reed-Solomon Encoder Block Diagram
Figure 1. Reed-Solomon Encoder Block Diagram

Description

The Amphion Reed-Solomon encoder megafunction provides compact, high-performance solutions for a wide range of applications.

The European digital video broadcast (DVB) standards provide system requirements for the broadcast of Motion Pictures Expert Group (MPEG)-2 transport packets via, for example, cable or satellite channels. Reed-Solomon error correction coding techniques are employed on the 188-byte MTS packets, with the capability to correct eight errors per transport packet. This correction requires the use of 16 parity symbols per MTS packet, resulting in a shortened Reed-Solomon codeword of N = 204, K = 188 (N is the number of symbols per codeword, K is the number of information symbols).

Amphion offers a range of Reed-Solomon encoder megafunctions, capable of operating up to 400 Mbps on Altera complex programmable logic devices (CPLDs). This megafunction is designed specifically for the requirements of the DVB standards.

The Reed-Solomon encoder megafunction assumes only the availability of a symbol rate clock and all operations in the encoder are timed with this clock. If a higher rate clock—for example a bit rate clock—is available, the clock can be used to reduce the gate count of the encoder.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Device Speed Grade Utilization Performance (fMAX) Parameter Setting
Logic Cells EABs (1)
EPF10K30A -1 199 0 88 Mbps N = 204, K = 188
8-bit symbols

Note:

  1. EABs = Embedded array blocks

Contact Information

For additional information, you can contact Amphion Semiconductor, Ltd. at:

Amphion Semiconductor, Ltd.
51 Malone Road
Belfast, BT9 6RY
Northern Ireland
Tel. +44 28 9050-4000
Fax +44 28 9050-4001

Email: info@amphion.com
URL: http://www.amphion.com

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