Altera Home Page
文档资料 许可
在线购买 下载

  主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买  
  器件   |   设计软件   |   IP   |   设计服务   |   开发套件及配件   |   资料  

 IP产品
   嵌入式处理器
   接口与外设
   DSP
          Filtering
          Modulation/Demodulation
          Transforms
          Encryption/Decryption
          Correlation
          Error Detection/Correction
          Video & Image Processing
          Audio Processing
          Arithmetic
          Signal Generation
          Additional Functions
          Consortiums
          资料
   通信
  
 About IP
      运用IP进行设计
      IP认证
      系统设计
      申请IP
  
 IP界合作伙伴
      AMPP计划
      AMPP核合作伙伴
  

Viterbi Decoder

from Amphion Semiconductor, Ltd.

Request Free Evaluation



AMPP Approved
OpenCore Support
DSP Builder Ready



Features

  • Soft decision decoder
  • High-speed applications, typically 45 millions of samples per second (MSPS) on continuous data stream
  • Compatible with other Amphion forward error correction (FEC) megafunctions
  • Dynamic support of R = 1/2 and R = 3/4
  • May be configured in terms of constraint length K, rate R, soft or hard decision
  • Simple interface allows easy integration into larger systems

Block Diagram

Figure 1 shows the block diagram for the Viterbi Decoder megafunction.

Figure 1. Block Diagram
Figure 1. Block Diagram

Description

The Amphion Viterbi decoder megafunction is a high-performance implementation suitable for a range of FEC applications. The megafunction may be used in conjunction with other FEC-related megafunctions available from Amphion to rapidly construct complete FEC solutions.

The megafunction has been developed in HDL and has been tailored specifically for Altera APEX and FLEX® architectures to obtain compact, high-performance implementations.

The basic megafunction assumes only the provision of a symbol rate clock. If a higher rate clock is available in the system, some of the hardware may be reused multiple times per data symbol period, reducing the overall hardware requirements. If the latency of the first sample is approximately 960 Clk x 4 cycles, a continuous data stream could typically be processed at 47 MSPS.

The Amphion Viterbi decoder megafunction can be rapidly configured for a wide range of specifications. The megafunctions have been developed using hardware description languages (HDLs), in a modular and parameterizable fashion. This design gives Amphion the capability to quickly configure a specific implementation to a user's specification by adding specific modules, such as the interleaver/deinterleaver and scrambler/descrambler.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Device Speed Grade Utilization Performance(fMAX) Parameter Setting
Logic Cells EABs (1)
EPF10K200E -1 2,846 4 19.5 ns,
51.28 MHz
K=7, R=1/2, soft decision decoder

Note:

  1. EABs = Embedded array blocks

Contact Information

For additional information, you can contact Amphion Semiconductor, Ltd. at:

Amphion Semiconductor, Ltd.
51 Malone Road
Belfast, BT9 6RY
Northern Ireland
Tel. +44 28 9050-4000
Fax +44 28 9050-4001
Email: info@amphion.com
URL: http://www.amphion.com  

  请填写反馈意见