Altera Home Page
文档资料 许可
在线购买 下载

  主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买  
  器件   |   设计软件   |   IP   |   设计服务   |   开发套件及配件   |   资料  

 IP产品
   嵌入式处理器
   接口与外设
   DSP
          Filtering
          Modulation/Demodulation
          Transforms
          Encryption/Decryption
          Correlation
          Error Detection/Correction
          Video & Image Processing
          Audio Processing
          Arithmetic
          Signal Generation
          Additional Functions
          Consortiums
          资料
   通信
  
 About IP
      运用IP进行设计
      IP认证
      系统设计
      申请IP
  
 IP界合作伙伴
      AMPP计划
      AMPP核合作伙伴
  

Turbo Product Code Decoder TC3400

from TurboConcept

Request Free Evaluation



AMPP Approved
OpenCore Support



Overview

The TurboConcept TC3400 is an iterative decoder of Turbo Product Codes (TPC). TPC is an attractive, advanced forward error correction (FEC) technique offering optimization for low implementation cost or very high throughput.

The TC3400 supports two-dimensional TPC codes, built using parity codes or Hamming codes. Optional support for high-performance Bose-Chaudhuri-Hocquenghem (BCH) codes (double-error correcting BCH family) is also available. The maximum code length and the optional BCH code support are chosen up-front as parameter options before core generation. This enables optimized core resource usage.

Two distinct throughput profiles are available:

  • Single decoder engine, TC3401, offering 40–50 coded Mbps on low-cost devices (Cyclone®  series)
  • Four decoder engines, TC3404, offering 300+ coded Mbps on high-performance devices (Stratix®  series)

A corresponding TPC encoder is available.  Please contact TurboConcept for more details.

Features

  • High error correction performance, especially for high code-rate applications
  • Efficient and scalable architecture
  • Constituent codes
    • Parity codes
    • Extended Hamming codes
    • Extended BCH double error-correcting codes
  • Row code sizes: 16, 32, 64, 128, or 256 bits
  • Column code sizes: 16, 32, 64, 128, or 256 bits
  • Shortened facilities to adjust packet size and coding rate
  • On-the-fly code changes
  • From 2 to 16 iterations
  • Reduces latency by bank-swapping option
  • Two selectable configuration interfaces
  • Selectable input data quantization width

Standard Deliverables

The TC3400 core is delivered as a synthesized netlist.  Deliverables include:

  • RTL model simulation libraries
  • MATLAB/C bit-true model
  • Testbench VHDL source code
  • Technical support and documentation

Contact Information

For additional information, contact TurboConcept at:

TurboConcept
40, rue Joseph Fourier
29280 Plouzane, France
Tel. +33 2 98 05 63 80
Fax +33 2 98 05 63 89
E-mail: info@turboconcept.com
http://www.turboconcept.com

  请填写反馈意见
  注册索取最新邮件通知