Altera Home Page
文档资料 许可
在线购买 下载

  主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买  
  器件   |   设计软件   |   IP   |   设计服务   |   开发套件及配件   |   资料  

 IP产品
   嵌入式处理器
   接口与外设
   DSP
          Filtering
          Modulation/Demodulation
          Transforms
          Encryption/Decryption
          Correlation
          Error Detection/Correction
          Video & Image Processing
          Audio Processing
          Arithmetic
          Signal Generation
          Additional Functions
          Consortiums
          资料
   通信
  
 About IP
      运用IP进行设计
      IP认证
      系统设计
      申请IP
  
 IP界合作伙伴
      AMPP计划
      AMPP核合作伙伴
  

CIC Compiler

from Altera Corporation

View Literature
Download Free Evaluation



OpenCore Plus Support
DSP Builder Ready



Version 7.0

  • Preliminary support for Cyclone® III Devices

Features

The Altera CIC Compiler implements a cascaded integrator-comb filter MegaCore® function and supports the following features:

  • Data ports are compatible with the Avalon® Streaming interface
  • Easy-to-use MegaWizard® interface for parameterization and hardware generation
  • Intellectual property (IP) functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
  • Support for OpenCore Plus evaluation
  • DSP Builder ready
  • Selectable decimation or interpolation filter types
  • Configurable number of stages (1 to 12)
  • Interpolation and decimation rate change factors (1 to 32,000)
  • Two differential delay options (1 or 2)
  • Configurable input data width (1 to 32 bits)
  • Configurable output data width (1 to full resolution data width)
  • Selectable output rounding modes (truncation, convergent rounding, rounding up, or saturation)
  • Single clock domain
  • Up to 1,024 channels
  • Hogenauer pruning support

General Description

CIC filters (also known as Hogenauer filters) are computationally efficient for extracting baseband signals from narrow-band sources using decimation, and for constructing narrow-band signals from processed baseband signals using interpolation.

Therefore, CIC allows for an economical hardware implementation of a filter, and is widely used in sample rate conversion designs such as digital down converters (DDC) and digital up converters (DUC). See Figures 1 and 2.

Figure 1. Three Stage Decimating CIC Filter Used in DDC

Figure 1. Three Stage Decimating CIC Filter used in DDC

Figure 2. Three Stage Interpolating Filter Used in DUC

Figure 2. Three Stages Interpolating Filter used in DUC

IP Evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive this suite of IP cores.

Performance & Resource Utilization

Typical expected performance and utilization figures for this core are provided in the User Guide.

Technical Support

For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.

Related Documents

  请填写反馈意见