from Altera Corporation
     |
Features and Description
The Altera® FIR Compiler MegaCore® function generates finite impulse response (FIR) filters customized for Altera devices. You can use the IP Toolbench interface to implement a variety of filter architectures, including fully parallel, serial, or multibit serial distributed arithmetic and multicycle fixed/variable filters. The FIR Compiler also includes a coefficient generator.
The FIR Compiler function speeds your design cycle by:
- Providing a fully integrated FIR filter development environment
- Generating the coefficients needed to design custom FIR filters
- Generating bit-accurate and clock-cycle-accurate FIR filter models in Verilog HDL, VHDL, and MATLAB
- Automatically generating the code required for the Quartus® II software to synthesize high-speed, area-efficient FIR filters of various architectures
- Creating Quartus II test vectors to test the FIR filter's impulse response
- Generating a VHDL testbench for all architectures
The FIR Compiler MegaCore function generated by this complier also:
- Supports a variety of distributed arithmetic and multiplier-based filter architectures up to 2,047 taps
- Generates MATLAB simulation models and testbench
- Generates a VHDL testbench for all architectures
- Is highly optimized for Altera device architectures
- Provides precision control of chip resource utilization
- Utilizes logic cells,M512, M4K, M-RAM, MLAB, M9K, or M144K blocks for data storage
- Utilizes logic cells, M512, M4K, MLAB, or M9K blocks for coefficient storage
IP Evaluation
Use the Altera OpenCore Plus Evaluation flow to test drive this core.
Performance and Resource Utilization
Typical expected performance and utilization figures for this core are provided in the FIR Compiler User Guide(PDF).
Technical Support
For technical support on this MegaCore function, please visit theAltera mySupport online issue tracking system. You may also search for related topics on this function in theAltera Knowledge Database.
