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FIR Compiler MegaCore Function

from Altera Corporation

View Literature
Download Free Evaluation



OpenCore Plus Support
DSP Builder Ready
Atlantic(TM) Compliant



Included in the IP Base Suite - FREE with Quartus® II Subscription

New in Version 7.0

  • Preliminary support for Cyclone® III devices

Features

  • Fully integrated finite impulse response (FIR) filter development environment
  • Highly optimized for Altera® device architectures including Stratix® II, Stratix II GX, Stratix GX, Stratix, HardCopy® II, HardCopy Stratix, Cyclone III, Cyclone II, and Cyclone devices
  • Precision control of chip resource utilization:
    • Utilizes logic cells, M512, M4K, M-RAM, MLAB, M9K, or M144K blocks for data storage
    • Utilizes logic cells, M512, M4K, MLAB, or M9K blocks for coefficient storage
  • Supports a variety of distributed arithmetic and multiplier-based filter architectures up to 2,047 taps.
  • Includes a built-in coefficient generator
  • Generates MATLAB simulation models and testbench
  • Generates a VHDL testbench for all architectures

General Description

The Altera FIR Compiler MegaCore® function generates finite impulse response (FIR) filters customized for Altera devices. You can use the IP Toolbench MegaWizard® interface to implement a variety of filter architectures, including fully parallel, serial, or multibit serial distributed arithmetic, and multicycle fixed/variable filters. The FIR Compiler also includes a coefficient generator.

The FIR Compiler function speeds your design cycle by:

  • Generating the coefficients needed to design custom FIR filters.
  • Generating bit-accurate and clock-cycle-accurate FIR filter models in Verilog HDL, VHDL and MATLAB.
  • Automatically generating the code required for the Quartus® II software to synthesize high-speed, area-efficient FIR filters of various architectures.
  • Creating Quartus II test vectors to test the FIR filter's impulse response.
  • Generating a VHDL testbench for all architectures. 

IP Evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive this suite of intellectual property (IP) cores.

Performance & Resource Utilization

Typical expected performance and utilization figures for this core are provided in the User Guide.

Technical Support

For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.

Related Documents

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