Inverse Discrete Wavelet Transform - BA114IDWT
Features
- Compliant with ISO/IEC 15444-1 Information Technology: JPEG2000 Image Coding System
- 2D recomposition with a programmable number of up to 5 recomposition levels
- Programmable lossless integer 5/3 or lossy floating point 9/7 filter
- Periodic symmetric border extension (according to JPEG2000 standard)
- Compact lifting scheme architecture with successive horizontal and vertical 1D recompositions
- 16-bit data path; fixed point 9/7 approximation
- Fully configurable tile size from 1 x 1pixel to up to 128 x 128 pixels; configurable tile offset
- Features an internal tile buffer for increased performance
- Easy slave coefficient interface through direct write access into internal tile buffer (SRAM type) and simple addressing of sub-bands to be placed in tile buffer
- Configurable pixel depth and sign up to 16 bits (practically limited to 12 bits for 5/3; 10 bits for 9/7)
- High-speed pixel interface allowing transfer of 1 pixel per clock cycle on an entire tile
- Easy master pixel interface through simple synchronous protocol
- Efficient pipelined architecture
- Fully synchronous design for easy integration with provided multicycle definitions for increasing performance
- Single clock design
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. BA114IDWT Block Diagram
Description
Figure 1 illustrates a simplified block diagram of the BA114IDWT intellectual property (IP), showing the internal modules and the interfaces. The BA114IDWT IP is a tile-level 2D inverse discrete wavelet transform (IDWT) engine recomposing a rectangular tile of any size up to 128 x 128 pixels from multiple frequency sub-bands. The BA114IDWT pixel interface can output an entire tile at high speeds with no interruption.
The core handles up to five multiple re-compositions internally. It reads the various sub-bands from its internal tile buffer where data has been previously stored through the coefficient interface by simply addressing the tile buffer. Sub-band data is arranged to facilitate sub-band access.
In addition to the coefficient interface, the configuration interface specification of the parameters is used for recomposing the tile. This eases the integration of the wavelet core into a processing chain where recomposition parameters come from a prior process. If needed, the configuration interface can easily be driven by a CPU.
Table 1 reports the efficiency results of the BA114IDWT IP core according to the number of recompositions. These results represent the actual sample throughput achieved by the IP core compared to the clock frequency. This number depends on the requested number of recompositions, because the filtering is recursively applied in order to generate each intermediate LL sub-band.
| Table 1. Throughput Efficiency |
| # decomp |
Efficiency |
| 0 |
96% |
| 1 |
96% |
| 2 |
76% |
| 3 |
72% |
| 4 |
71% |
| 5 |
70% |
Finally, the BA114IDWT IP core is driven by a simple command and control interface to start and monitor the process.
The following sections describe the modules constituting the BA114IDWT core as shown in Figure 1.
Coefficient Data Router
This module fetches the coefficient data needed to apply the 2D inverse discrete wavelet transform (IDWT) from the internal tile buffer.
1D Horizontal and Vertical IDWT
Both modules perform a single-level IDWT. The first module achieves horizontal recomposition on the tile lines, while the second module achieves vertical recomposition on the tile columns. When combined, both processes result in bidimensional inverse wavelet transforms. These modules feature a 16-bit data path. They implement state-of-the-art periodic symmetric border extension according to the programmed tile size (compliant with JPEG2000).
Pixel Data Router and Level Shifter
The pixel data router module reorders data coming out of the 1D vertical wavelet filter. It also manages multilevel recomposition by updating the intermediate LL buffers situated in the tile buffer. The level shifter performs all operations required in order for the pixel data to comply with the configured settings. This implies level-shifting unsigned pixel data and removing fractional bits for 9/7 fixed point processing.
Sequencer
This module organizes the internal BA114IDWT pipeline. It communicates with the host through a simple Command&Control interface to start processing and monitoring the re-composition process. The BA114IDWT is driven at tile level and performs complete multi-level re-composition, sending the results at the pixel interface, and then going back to an idle state.
Device Utilization & Performance
Table 2 lists the typical device utilization results for the megafunction.
| Table 2. Typical Device Utilization |
| Target Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
Memory |
I/O Pins |
| Stratix® EP1S20F484C5 |
-5 |
4,050 |
2 MRAM
28 M4K |
99 |
123 MHz |
- |
| HardCopy© HC1s30-F780 |
- |
- |
- |
- |
163 MHz |
- |
Deliverables
- Encrypted netlist w/ license file
- Data sheet
- Test bench
Contact Information
For additional information, contact Barco Silex at:
Barco Silex
Scientific Park
Rue du Bosquet 7
B-1348 Louvain-la-Neuve
Belgium
Tel: +32 10 486 403
Fax: +32 10 454 636
E-mail: barco-silex@barco.com
URL: www.barco-silex.com
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