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Fast Color JPEG Decoder

from Barco Silex

Request Free Evaluation



AMPP Approved
OpenCore Support
DSP Builder Ready



Features

  • High-speed sustained single clock cycle per pixel component decoding
  • Single clock cycle Huffman decoding
  • APEX 20KC and APEX II optimized support
  • 100% baseline ISO/IEC 10918-1 JPEG compliance for gray-scale images (single- and multi-scan formats) extending to effective 256-scan support
  • Full header parsing capability and automatic on-the-fly Huffman and quantization tables reprogramming from header data
  • Header error catching features
  • Full JPEG format and abbreviated format support, including restart markers
  • Simple first-in, first-out (FIFO) interfaces for compressed data (32 bits) and pixel interfaces (8 bits)
  • Simple CPU interface for decoder programming
  • Easy-to-use status and control interface through six internal registers
  • Programmable external interrupt for event follow-up
  • Four entropy tables (two DC, two AC) and four quantization tables
  • Burst image-sequence decoding support for images with identical tables
  • 8 bits/pixel
  • 8 x 8 block-format pixel output with classical scan order (row by row from left to right)
  • Fully synchronous hardware design
  • Fully stallable compressed-data interface; stallable pixel interface on a block-by-block basis
  • IEEE 1180-1990 compatible IDCT for number precision requirements

Block Diagram

Figure 1 shows a block diagram of the megafunction.

Figure 1. Block Diagram

Figure 1. Block Diagram

Description

The JPEG IP core is intended for high-speed decoding of gray-scale, color, or multi-scan images coded with ISO/IEC 10918-1 baseline coding standard. The decoder supports all features of the baseline standard, including restart markers and full header parsing. It is able to decode abbreviated-format or full-format images, automatically extracting the quantization and entropy tables.

With its autonomous behavior, simple FIFO-like interfaces, and 100% synchronous structure, you can integrate this IP core in a complex system with little effort. This is reinforced by the stand-alone ability of the decoder that allows to instantiate it in systems without CPU intervention.

Contact Barco Silex for more information.

Device Utilization and Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Target Device Speed Grade Utilization Performance
(fMAX)
Parameter Setting
Logic Cells ESBs I/O Pins
EP20K400CF672 -7 10174 66 78 55 MHz Contact Barco Silex
EP2A15F672C -7 10086 44 78 58 MHz Contact Barco Silex

Deliverables

  • Design encrypted files
  • VHDL testbenches
  • VHDL/Verilog instantiation templates
  • User guide documentation

Contact Information

For additional information, contact Barco Silex at:

Barco Silex
Scientific Park
Rue du Bosquet 7
B-1348 Louvain-la-Neuve
Belgium
Tel: +32 10 486 403
Fax: +32 10 454 636
E-mail: barco-silex@barco.com
URL: www.barco-silex.com  

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