from Barco Silex
     |
Features
- Compliant with baseline JPEG (ISO/IEC 10918-1)
- Support for color images (single- and multi-scan format)
- Single clock cycle per pixel component encoder
- Single clock cycle Huffman encoding
- Full header building capability
- Automatic internal Huffman and quantization table programming based on
header data - Support for full-format and abbreviated-format, including restart markers and restart interval
- One-pass encoding scheme with bit rate regulation if enabled
- Simple FIFO interfaces for compress-data and pixel-data interfaces
- Simple CPU interface for encoder and header programming
- Easy-to-use status and control interface
- Programmable external interrupt for event follow-up
- Four entropy tables (two DC and two AC) and four quantization tables
- Burst image-sequence encoding support for images with identical tables
- 8x8-block pixel input with classical scan order
- Fully scalable compressed data and pixel interfaces
- Fully synchronous hardware design
- Throughputs ranging from sub CIF 25 MHz to SDTV to HDTV
Block Diagram
Description
The BA116 JPEG Encoder intellectual property (IP) core is for high-speed encoding of grayscale, color, or multi-scan images using the ISO/IEC 10918-1 baseline coding standard. The encoder supports all features of the baseline standard, including restart markers, DNL markers, user-definable comments, and application markers.
The BA116 JPEG Encoder is able to encode abbreviated-format or full-format images. If preferred, pre-defined default entropy and quantization tables are available. Its autonomous behavior, simple FIFO-like interfaces, and 100-percent synchronous structure allow easy integration of the IP into complex systems with little effort. The ease of integration of this powerful IP core is reinforced by the standalone ability of the encoder that can be used in systems with very little CPU intervention.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction | |||||
| Target Device | Speed Grade | Utilization | Performance (fMAX) |
||
|---|---|---|---|---|---|
| Logic | M9K | DSP18 | |||
| EP3C40C | -6 | 16,782 logic elements (LEs) | 12 | 2 | 105 MHz |
| EP2AGX95C | -4 | 3,371 adaptive logic modules (ALMs) | 12 | 2 | 175 MHz |
Deliverables
- Design encrypted files
- VHDL testbenches
- VHDL instantiation templates
- Altera Quartus® II software implementation example
- User guide documentation
Contact Information
For additional information, contact Barco Silex at:
Barco Silex
Scientific Park
Rue du Bosquet 7
B-1348 Louvain-la-Neuve
Belgium
Tel: +32 10 486 403
Fax: +32 10 454 636
E-mail: barco-silex@barco.com
URL: www.barco-silex.com
