Digital Downconverter (DDC) Reference Design
from Altera Corporation
Introduction
Much of the signal processing performed in modern wireless communications systems takes place in the digital domain, which greatly increases processing demands of modern digital modulator/demodulator applications. The high data rate, parallel processing capabilities of Altera programmable logic devices makes them an attractive solution for baseband/intermediate frequency (IF) digital signal processing (DSP) applications.
By combining drop-in DSP cores from Altera's extensive intellectual property (IP) portfolio with Altera® Stratix™ devices, complex high performance DSP designs can be implemented in a relatively short period of time. Altera provides a direct digital downconverter (DDC) reference design with the DSP Development Kit, Stratix Edition for use as either a design starting point or an experimental platform.
A DDC demodulates a signal and then decimates it down to baseband. Designers typically use DDCs in digital receivers, in front-end demodulators and 3G wireless UMTS systems. The signal coming to the receiver often contains extra noise, which is removed by filtering and pulse shaping. The Altera DDC reference design consists of numerically controlled oscillators (NCOs), FIR filters, and open-source Verilog HDL glue logic that supports 8 independent channels. The target device on the Stratix EP1S25 DSP development board is the EP1S25F780C5. The target device on the Stratix EP1S80 DSP development board is the EPS1S80B956C6.
The DDC modem reference design provides the following features:
- Input sample rate of 92.16 millions of samples per second (MSPS)
- 8 UMTS channels
- Decimation factor of 24
- 14-bit input samples
- 16-bit output samples
- 0.02-Hz tuning resolution
- > 80 dB far band rejection
- > 110 dB spurious free dynamic range (SFDR) using an 18-bit NCO
- Nyquist filtering for QPSK or QAM symbol data
- Signal generator utility to create a modulated input signal
- Spectral display utility to display the filter frequency response
Resource Utilization
The resource utilization is 22,000 LEs, 8 DSP blocks, and 208 M512 RAM blocks, 12 M4K RAM blocks, and 2 M-RAM blocks.
Technical Support
For technical support on this reference design, please visit the Altera mySupport on-line issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.
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