Turbo Encoder Co-processor Reference Design
You have to request this Altera® reference design from your Altera representative.
Introduction
The turbo encoder co-processor reference design is for implemention in an Stratix™ DSP development board that is connected to a Texas Instruments C6711 DSP Starter Kit (DSK). The DSK has a 32-bit external memory interface (EMIF) and a 16-channel enhanced DMA (EDMA) controller. The design of the DSK limits the use of the EMIF to asynchronous mode only.
The reference design connects the DSK processor’s EMIF to Altera’s Turbo Encoder MegaCore funtion. The reference design includes an Avalon™ interface (master), which allows you to connect other functions. The Avalon bus is a simple bus architecture designed for connecting on-chip processors and peripherals together into a system-on-a-programmable chip (SOPC). The Avalon bus is an interface that specifies the port connections between master and slave components, and specifies the timing by which these components communicate.
Altera supplies the reference design as Verilog HDL source code. The reference design includes a testbench that allows you to test the Verilog HDL source code.
The purpose of this reference design is to demonstrate that Altera Stratix and Cyclone™ devices are suitable in performance and capacity to implement digital signal processing (DSP) functions as co-processors.
Technical Support
For technical support on this reference design, please visit the Altera mySupport on-line issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.
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