Altera Home Page
文档资料 许可
在线购买 下载

  主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买  
  器件   |   设计软件   |   IP   |   设计服务   |   开发套件及配件   |   资料  

 IP产品
   嵌入式处理器
   接口与外设
   DSP
          Filtering
          Modulation/Demodulation
          Transforms
          Encryption/Decryption
          Correlation
          Error Detection/Correction
          Video & Image Processing
          Audio Processing
          Arithmetic
          Signal Generation
          Additional Functions
          Consortiums
          资料
   通信
  
 About IP
      运用IP进行设计
      IP认证
      系统设计
      申请IP
  
 IP界合作伙伴
      AMPP计划
      AMPP核合作伙伴
  

Up Converter

from CommStack, Inc.

Request Free Evaluation



AMPP Approved
OpenCore Support
DSP Builder Ready



Features

  • Designed for maximum speed (fMAX > 140 to 270 MHz)
  • Optimized for 10-bit input and output datapath word widths (others on request)
  • Tunable IF output frequency (with parameterized frequency word width)
  • Optimized for Altera® ACEX™ 1K, FLEX® 10K, APEX™ 20K, and Mercury™ devices
  • Ideal for the following applications:
    • Digital modulators/demodulators
    • Direct digital IF output
    • Wireless & wired telecommunications systems

Block Diagram

Figure 1 shows the block diagram for the megafunction.

Block Diagram

Description

The CommStack Up Converter megafunction converts a complex baseband digital signal to a "direct IF output" real digital signal at an IF frequency which may be either fixed or specified by other circuitry in real time.

This function is often used as the final stage of digital modulator designs, e.g., in DOCSIS, LMDS, or MMDS applications. The input signal may be in any of a variety of formats, including AM, BPSK, QPSK, GMSK, 8-PSK, OFDM, or 16- to 256-QAM.

The datapath is optimized for 10-bit inputs and outputs, but other datapath word widths may be implemented on a customized basis at nominal cost. Additional precision is implemented in the multipliers and output adder in order to maintain 10-bit accuracy in the product.

The digital IF carrier frequency input is parameterized to support frequency word widths of 10 bits to 40 bits or more. The frequency input may be updated in real time, i.e., as a result of a digital phase-locked loop (PLL) tracking a reference frequency input.

With performance from 140 Mbps to over 270 Mbps, depending on device family, CommStack's Up Converter megafunction provides the high speed often required in direct IF output designs.


Device Utilization Examples

Table 1 lists the typical device utilization results for the megafunction.

Table 1: Typical Device Utilization for Megafunction
Device Speed Grade Logic Cells EABs (1) fMAX (typical) Frequency Word Size
EP1K100,
EPF10K100E
-1 546 2, 4 142 MHz 36
EP20K100E -1 562 2 144 MHz 36
EP20K100C -7 562 2 180 MHz 36
EP1M120 -5 562 2 276 MHz 36

Note:
  1. EABs = Embedded array blocks
Contact Information

For additional information, contact

CommStack, Inc.
72 Fairfax Avenue
Atherton, CA 94027

Phone: (650) 701-0939
E-mail: info@commstack.com
Internet: http://www.commstack.com

  请填写反馈意见