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Commsonic QAM (DVB-C/J.83) Modulator

from Commsonic

Request Free Evaluation



AMPP Approved
OpenCore Support



Features

  • Compliant with DVB-C (EN 300 429) and ITU J.83 Annexes A, B and C including DOCSIS 1.1/2.0
  • 16, 32, 64, 128 and 256 QAM
  • Arbitrary symbol rate up to a quarter of the applied master clock frequency
  • Scalable architecture supports from one to four channels per core and multiple cores per FPGA
  • Programmable or constant-coefficient channel filter allows trade-off between flexiblity and core size
  • Modulation accuracy
  • Configurable radio interface supports direct conversion and/or superhet transmitters
  • Configurable interleaver operates from either internal or external memory
  • Synchronous parallel transport stream interface

Block Diagram

Figure 1. CMS0024 Cable (QAM) Modulator Block Diagram

Figure 1. Commsonic QAM (DVB-C/J.83) Modulator

Adobe Acrobat PDF Icon Click for full detail (60KB)

Figure 1 shows a block diagram of this megafunction.

Description

The CMS0024 Cable (QAM) Modulator is fully compliant with the European, US, and Japanese downlink cable standards DVB-C and J.83, providing all the necessary functions between transport stream input and QAM output.

The core can be configured to support from one to four FDM channels with additional (independent) channels accommodated by the instantiation of multiple single or multi-channel cores per FPGA.

Multi-channel J.83B designs can operate either from internal memory (short interleaving modes) or from shared external memory (long interleaving modes) by means of an arbitrating access controller.

A range of synthesis options allows the core to be tailored for any particular application. Commsonic offers transport stream interface cores to perform rate adaptation (NULL packet stuffing) and retiming (PCR restamping).

Typical applications of the CMS0024 include head-end video and broadband data transmissions systems (CMTS), cable modem test equipment and point-to-point (PTP) or point-to-multipoint microwave radio links.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for Altera Megafunctions
Device Configuration Logic Elements (LEs) 9x9 Multipliers M4K RAM
EP2C20 1-channel DVB-C 11k, 31% 52, 100% 36, 69%
EP2C35 4-channel J.83B (short interleave) 27k, 82% 70, 100% 100, 95%
EP2C35 4-channel J.83B (long interleave) external RAM 27k, 82% 70, 100% 36, 34%
EP2C70 1-channel J.83B (long interleave) 9k, 13% 84, 28% 161, 37%
EP2C70 8-channel J.83B (short interleave) 43k, 64% 288, 96% 192, 76%

Deliverables

  • Core netlist or encrypted VHDL for Quartus® II software
  • Verification Environment
    • Testbench pre-compiled simulation libraries for ModelSim® tool
    • VHDL test scripts
  • Documentation
    • User guide
  • One year of technical support and maintenance

Contact Information

For additional information, contact Commsonic at:

Commsonic Limited
St Johns Innovation Centre
Cowley Road
Cambridge CB4 0WS
ENGLAND
Tel: +44(0)1223 421845
Fax: +44(0)1223 871071
Email: info@commsonic.com
URL: http://www.commsonic.com

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