Linear Feedback Shift Register
Features
- Programmable pattern length
- Automatic resizing and feedback selection
- Programmable initial value (IV)
- Optimized for the Altera APEXTM 20K, FLEX® 10K, and FLEX 8000 device architectures
- Applications
- Encryption/decryption
- Direct sequence spread spectrum
- Pseudo-random number (PN) generation
- Scrambler/de-scrambler
- Built-in self test
Block Diagram
Figure 1 shows the block diagram for the linear feedback shift register megafunction.
| Figure 1. Block Diagram |
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Description
A linear feedback shift register (LFSR) megafunction is based on linear XOR or XNOR feedback logic in which the initial value of the shift register, shift register taps, and feedback logic determines the output sequence. This scheme allows the user to load the shift register with an initialization sequence. The shift register taps are combined with XOR or XNOR logic and then fed back into the shift register input.
The shift register size (m) is equal to length + 1, where length is an integer between 1 and 31. The shift register produces a sequence of
2 m - 1 bits. For example, a shift register size of 32 produces a shift register sequence of 232 - 1 bits and is specified by setting the length input to 31. The length input is synchronous to the rising edge of the clock. When a clock edge loads the length input, the megafunction will automatically reconfigure the shift register's size.
The load input initializes the contents of the shift register. Whenever load is asserted, the megafunction configures itself to a normal shift register size of 32. The desired initial value will be loaded through the shift_in input using 32 clock cycles. Because the length value is ignored when load is asserted, length can be asserted any time before load de-asserts. The load input can be de-asserted after the 32nd rising clock edge. The next rising edge of the clock would then configure the shift register size and feedback logic and initialize the length sequence.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs Note (1) |
| EPF10K50V |
-1 |
338 |
0 |
103 MHz |
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| EPF6016 |
-2 |
318 |
0 |
95 MHz |
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| EPM7128E |
-7 |
103 |
0 |
113 MHz |
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Note:
- EABs = Embedded array
blocks
Contact Information
For additional information, you can contact contact Nova Engineering, Inc. at:
Nova Engineering, Inc.
5 Circle Freeway Drive
Cincinnati, OH 45246-1105
Tel. 513-860-3456
Fax 513-860-3535
E-mail: info@nova-eng.com
WWW: http://www.nova-eng.com
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