DFP2INT Floating-Point-to-Integer Pipelined Converter
Features
- Full IEEE-754 compliance
- Single-precision real input numbers
- Double word output numbers (up to 4 bytes)
- Simple interface
- No programming required
- Two levels of pipelining
- Full accuracy and precision
- Results available at every clock
- Overflow, underflow, and invalid operation flags
- Fully configurable
- Fully synthesizable, static-synchronous design with no internal tri-states
Description
The DFP2INT megafunction supports single-precision real numbers and double-word integers up to 4 bytes. The convert operation is pipelined to two levels, and the input data is fed in at every clock cycle. The first result appears after two clock periods of latency, and the subsequent results are available at each clock cycle.
Block Diagram
Figure 1 shows the block diagram for the DFP2INT megafunction.
Figure 1. Block Diagram for DFP2INT Megafunction
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Parameter Setting |
| Logic Cells |
Performance
(fMAX) |
| FLEX® EP10K100E |
-1 |
394 |
61 MHz |
Contact Digital Core Design |
| APEXTM EP20K100E |
-1 |
367 |
75 MHz |
Contact Digital Core Design |
| ACEX® EP1K100 |
-1 |
394 |
62 MHz |
Contact Digital Core Design |
Contact Information
For additional information, contact Digital Core Design at:
Digital Core Design
Wroclawska 94
41-902 Bytom, Poland
Tel. +48 32 282 82 66
Fax +48 32 282 74 37
E-mail: info@dcd.com.pl
URL: www.dcd.com.pl
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