Floating-Point FFT Processor (IEEE 754 Single Precision) Cores
from Altera Corporation
This Altera® function may require
customization services prior to use. You can use the "Request Free Evaluation"
link on this page to contact Altera for more information.
Features
- Radix 4 and radix 2 implementations
- IEEE 754 single precision data and twiddle ROMs and RAMs
- 1 sign bit
- 8 exponent bits
- 23 mantissa bits
- Highly parameterizable—any length (power of 2) FFT
can be implemented
- Very high performance (< 30 µs for radix 4, 1K FFT)
- Interfaces to on-chip or off-chip memory
- Optimized for Altera® Stratix™
device family—uses the Stratix DSP blocks and TriMatrix™
memory
- Two utilities provided with the core
- .hex file generator for twiddle ROMs
- MATLAB M files to generate VHDL testbenches and compare simulation
results to MATLAB double precision FFT
- Two top-level reference designs provided with the core
General Description
The floating-point fast Fourier transform (FFT) processor calculates FFTs with
IEEE 754 single precision (1 sign bit, 8 exponent bits, and 23 mantissa bits)
accuracy. The processor uses extended precision arithmetic (1 sign bit, 8 exponent
bits, and 32 mantissa bits) internally for higher accuracy. The floating point
FFT processor radix 2 and the radix 4 cores can implement any powers of 2 length
of FFT. The cores are optimized for the Stratix™ device family
and take advantage of the Stratix DSP blocks and M-RAM blocks.
You can parameterize the number of points at compile time. There are two versions
of the cores in each package, one version is optimized for internal device memory
and the other for memory external to the device. Top-level reference designs,
with open source code, allow you to integrate the core into your system.
The cores are designed for simulation with the ModelSim simulator (version
5.6a) and synthesis using the Quartus®
II software. Testbench generation and analysis utilities (MATLAB-based) are
included for verifying the core in both environments.
Performance
The performance of the FFT is dependant on two factors: the clock rate of the
FFT system, and the number of clocks required to calculate the FFT.
The number of clocks required is given by:
Number of passes required × number of clocks per
pass
where:
number of passes = log2(points) (for radix 2)
number of passes = log2(points)/2 (for radix 4)
number of clocks per pass = points + 32 + datadelay
Table 1 shows the performance and size of the radix 4 and radix 2 core with
a Stratix EPS1S10F484C5 device.
| Table 1: Performance & Size |
|
Device
|
Radix
|
Points
|
LEs
|
DSP Blocks
|
Memory (KBits)
|
fMAX (KBits)
|
Transform Time (µs)
|
| EPS1S10F484C5 |
4
|
1,024
|
5,427
|
4
|
72
|
166
|
30
|
| EPS1S10F484C5 |
2
|
1,024
|
2,713
|
2
|
72
|
166
|
60
|
Licensing
A license is not required to perform the following trial operations using your
own custom logic:
- Instantiation
- Place-and-route
- Static timing analysis
- Simulation on a third-party simulator
When you are ready to generate programming files, you need to obtain licenses
through your local Altera sales representative.
Technical Support
For technical support, please visit the Altera
mySupport on-line issue tracking system. You may also search for related
topics on this core in the Altera
Knowledge Database.
|
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