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主页 > 产品 > IP > 接口与外设 > Additional Functions > BitSim Accelerated Display Graphics Engine (BADGE) 打印此页 订阅电邮新闻 BitSim Accelerated Display Graphics Engine (BADGE) from Bitsim Features Flexible interfaces for host, display, and memory Configurable number-graphics processing units (GPUs) work simultaneously and can be chosen independently Modular design of BitSim Accelerated Display Graphics Engine (BADGE) combined with Altera® FPGA reconfigurability enables easy adjustments to accommodate different requirements such as a new display manufacturer, a bigger display or different resolution, or alternate versions to support market-specific requirements Adaptable for a wide range of processors, including Altera Nios® II embedded processors Adding external memory (for graphics and/or video storage), a display, and a control (host) interface to the FPGA, results in a flexible and future-proof display platform The data bus between the FPGA and the display memory is 32-bits wide, enabling two simultaneous pixel operations/accesses BADGE implementation in an Altera Cyclone®   II EP2C5 device offers the following: Display memory SDRAM of 16M x 32 bits Displays 1,024 x 768, 16 bits per pixel, and 60 frames per second System clock frequency of 100 MHz; display clock frequency of 50 MHz Block Diagram Figure 1. BADGE Block Diagram Description Graphics display controller requirements sought by hardware developers grow more and more complex. Using an Altera FPGA-based solution increases the ability to customize the solution to the specific product and provides a platform for easy development of next-generation products with additional or more advanced display features. Low-cost FPGAs, such as Cyclone II devices, provide a cost-effective way to implement standard display functions, in some cases delivering lower cost than existing ASSP-based solutions.  Anticipating the requirements of next-generation products, BitSim developed the BitSim Accelerated Display Graphics Engine (BADGE).  An FPGA-based graphics controller intellectual property (IP) module, BADGE supports up to 4,096 x 4,096 pixel resolution. The modular nature of BADGE enables you to select exactly which processing units and interfaces you need to implement a specific application. For example, BADGE Light, which provides the minimum set of capabilities, combined with a Nios II processor, occupies less than 3,000 logic elements (LEs), the basic building block of Altera FPGAs. You can implement a complete BADGE solution, including a Nios II processor, in the smallest of Altera’s Cyclone II FPGAs, resulting in a very low-cost solution. Table 1 lists some of the common BADGE configurations and their functionality. Table 1. Common BADGE Configurations BADGE Configuration Functionality BADGE Light Display controller module (off-loads host) Host direct pixel write operations support Memory direct access GPU for frame buffer support SDRAM video memory support 32-bit buses Up to 24-bit color depth BADGE Video BADGE Light platform Video processing unit for analog video input Analog video 576 x 720 pixels at 25-Hz frame rate Video shown as sub window on display Graphics and text overlay BADGE 2D BADGE Light platform Simple pixel drawing GPU, character GPU, and rectangle GPU 2D acceleration such as BitBLT with ROP, line drawing engine, text (with different fonts, sizes, and so on) Hardware cursor Table 2 shows the Altera FPGA device utilization of these BADGE configurations and a host Nios II processor, including their logic element and I/O pin requirements (for memory interface, LVTTL, LVDS, and so on). It also shows the smallest Cyclone II device required for implementation, and the remaining logic elements and I/O pins available in the device for additional functions. Table 2. Altera Device Utilization BADGE Configuration Altera FPGA Device Utilization (1) I/O Pins Needed Smallest Cyclone II Device Required Additional Logic Available Additional I/O Pins Available BADGE Light 2,909 LEs 88 EP2C5 1,699 LEs 70 BADGE Video 4,843 LEs 163 EP2C8 3,413 LEs 19 BADGE 2D 5,780 LEs 163 EP2C8 2,476 LEs 19 Note to Table 2: Includes the Nios II processor Deliverables Documentation (includes data sheet and user guide)  Design file formats VHDL or netlist Constraints file verification Testbench Command file Reference design (hardware platform and test software) available (not included) Simulation tool (ModelSim® script) Support provided by BitSim AB Related Links Gain Flexibility, Lower Costs in Display Control Through Integration with FPGAs White Paper (PDF) For additional information, contact BitSim at: BitSim AB St. Eriksgatan 33 SE-112 39 Stockholm, Sweden Tel: (+46) 8 54 55 56 00 Fax: (+46) 8 54 55 56 11      Email: fpga@bitsim.com URL: www.bitsim.com 给本页评分

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