MCAN2D1 CAN 2.0 Network Controller
Features
- Designed to full CAN 2.0—both 2.0A (equivalent to CAN 1.2) and 2.0B
- Supports 11-bit and 29-bit identifiers
- Supports bit rates from less than 125K baud to more than 1M baud
- 64-byte Receive FIFO buffer
- 8-bit synchronous PVCI-compatible CPU interface for easy connection to a range of processors. (Virtual Component Interface, as defined by VSIA; OCB 2 version 1.0)
- Acceptance filtering
- Software-driven bit-rate detection allowing hot plug-in support
- Listen-Only and Self-Reception modes
- Self-Test option
- Interrupt generated for each bus error
- Arbitration lost interrupt with record of bit position
- Read/Write Error counters
- Programmable error limit warning
- Broadly compatible with Philips SJA1000 in its PeliCAN mode
- Verified against Bosch CAN2.0 test suite
- Optimized for use with Altera® Nios® embedded processor
Block Diagram
Figure 1 shows the block diagram for the Mentor Graphics MCAN2D1 CAN 2.0 Network Controller.
| Figure 1. Block Diagram |
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Description
The MCAN2D1 CAN 2.0 Network Controller from Mentor Graphics is an implementation of the Mentor MCAN2 soft core as an encrypted netlist for Altera programmable logic devices (PLD). The MCAN2 is a stand-alone controller for a controller area network (CAN). It provides an interface between a microprocessor and a CAN bus which carries out all the actions of data encoding/decoding, message management, bit timing and re-synchronization involved in transmitting and receiving data over a controller area network. The MCAN2 implements the BOSCH CAN message transfer protocols 2.0A and 2.0B. Specification 2.0A is equivalent to CAN 1.2 and covers standard message formats (11-bit identifiers); specification 2.0B covers both standard and extended message formats (both 11-bit and 29-bit identifiers). The MCAN2 is broadly compatible with a Philips SJA1000 working in its PeliCAN mode. Its CPU interface is compatible with the peripheral virtual component interface (defined by VSIA) for ease of connection to a range of microprocessor buses.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| APEX™ 20KC |
-1 |
5619 |
0 |
32.46 MHz |
Fixed Configuration |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Mentor Graphics at:
Mentor Graphics
1001 Ridder Park Dr.
San Jose, CA 95131
Tel. (408) 487-7039
Fax (408) 487-7380
Email: mentor_ip@mentor.com (Netlist Sales)
URL: www.mentor.com/products/ip/index.cfm
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