PE-MACMII - 10/100 Ethernet Media Access Controller
Features
- Fully compliant with IEEE 802.3z standard
- Supports 802.3x full-duplex flow control and half-duplex back pressure
- Supports single- and multi-mode fiber optic devices
- Supports 10 or 100 Mbps MII based PHY devices including:
- 10BASE-T
- 100BASE-TX
- 100BASE-FX
- 100BASE-T4
- Expanded statistics vectors for remote network monitoring (RMON) and Etherstat applications
- Flexible transmit and receive frame options
- Frame address detection
- Supports control frames, with additional support for proprietary control frames
- 32-bit, 31.25-MHz design
- Transmit and receive block-specific resets
- 32-bit host data transfer interface
- MII management block for interfacing with PHY devices
- Verilog hardware description language (HDL) functional testbench
- Proven in silicon and currently shipping in multiple products
- Supporting modules available
- Verilog HDL register transfer level (RTL) source code available
- Proven in silicon and currently shipping in multiple products
- Supporting modules available
- Verilog HDL RTL source code available
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. PE-MACMII - 10/100 Ethernet Media Access Controller Block Diagram
Description
The PE-MACMII module is a technology module that may be incorporated in a design to implement the Ethernet media access control (MAC) protocol defined by the IEEE standard. The PE-MACMII module consists of five sub-blocks. These sub-blocks are the transmit and receive portions of the Ethernet MAC plus the MAC control sub-layer block. In addition, there is a host interface block, and the MII management block. There are many different possible applications, including network interface designs, Ethernet switching designs, and test equipment designs.
The transmit function (TFUN) is responsible for generating MII nibble data streams, as defined in IEEE 802.3u, in response to packet byte streams supplied from the host system. The TFUN block performs the required deference and back-off algorithms and reports per-packet statistics. Excessive deferrals, maximum collisions, oversized packets and input under-run conditions will be reported in the transmit statistics vector.
The receive function (RFUN) is responsible for interpreting MII nibble streams, as defined in IEEE 802.3u, and supplying well-formed frame-byte streams to the host system. The RFUN searches for the start of frame delimiter at the beginning of the packet, qualifies the frame length, verifies the cyclic redundancy check (CRC), and observes any dribble nibbles, received code violations, received events, or carrier events that may occur. After a packet has been sent out from the RFUN, a receive status vector (RSV) is output and the vector indicator (RSVP) is pulsed.
The MCS block performs the functions outlined in IEEE 802.3x, Clause 31 "MAC control" and Annexes 31A and 31B. Clause 31 introduces the optional MAC control sub-layer to the popular layer stack. This sub-layer provides for real-time control and manipulation of the MAC operation. The clause defines MAC control frames distinguishable by their unique length/type field identifier (88-08).
The MIIM block communicates between the host processor and an external MII physical device by means of a two-wire interface.
The HOST block provides a central repository for register logic and a 16-bit control and configuration interface for the PE-MACMII.
Device Utilization Example
Table 1 lists the typical device utilization results for the PE-MACMII megafunction.
| Table 1. Typical Device Utilization |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) (2) |
Parameter Settings |
| Logic Cells |
EABs/ESBs (1) |
| APEX 20KE |
-1 |
1,784 |
0 |
25 MHz |
Contact Mentor Graphics |
| FLEX 10KE |
-1 |
2,296 |
0 |
25 MHz |
Contact Mentor Graphics |
| ACEX 1K |
-1 |
2,291 |
0 |
25 MHz |
Contact Mentor Graphics |
Notes:
- EABs = Embedded array blocks
ESBs = Embedded system blocks
- An fMAX of 25 MHz is all that is required to meet the IEEE 802.3 specification for 100 Mbps operating mode, the actual fMAX achieved will generally be higher.
Deliverables
Encrypted electronic design interface format (EDIF) netlist:
- Quartus® II software constraint files
- Design documentation
- Verilog functional testbench
Contact Information
For additional information, contact:
Mentor Graphics
1001 Ridder Park Dr.
San Jose, CA 95131
Tel. (509) 465-3523
Fax (408) 487-7380
Email: mentor_ip@mentor.com (Netlist Sales)
URL: www.mentor.com/products/ip/index.cfm
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