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PE-MCXMAC - 10/100/1000 Ethernet MAC

from Mentor Graphics

Request Free Evaluation



AMPP Approved
OpenCore Support
SOPC Builder Ready



Features

  • Fully compliant with the IEEE 802.3 standard
  • Supports IEEE 802.3x full-duplex flow control and half-duplex back pressure
  • Supports single- and multi-mode fiber optic devices
  • Supports 10- or 100-Mbps media-independent interface (MII)-based physical layer (PHY) devices including:
    • 10Base-T
    • 100Base-TX
    • 100Base-FX
    • 100Base-T4
  • Supports 1,000-Mbps gigabit media-independent interface (GMII)-based PHY devices
  • Expanded statistics vectors for remote network monitoring (RMON) and Etherstat applications
  • Flexible transmit and receive frame options
  • Frame address detection
  • Supports control frames, with additional support for proprietary control frames
  • 8-bit, 125-MHz design
  • Transmit and receive block-specific resets
  • 32-bit host data transfer interface
  • MII management (MIIM) block for interfacing with PHY devices
  • Verilog hardware description language (HDL) functional testbench
  • Proven in silicon and currently shipping in multiple products
  • Supporting modules available
  • Verilog HDL register transfer level (RTL) source code available

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. PE-MCXMAC Block Diagram

Figure 1. PE-MCXMAC Block Diagram

Description

The PE-MCXMAC is an 8-bit media access control (MAC) module with GMII that is fully compliant with the IEEE 802.3 standard and its supplements. The system interface presents frames to be transmitted by the MAC. Frames may or may not be padded or contain the frame check sequence (FCS) field. Depending upon the programmed configuration internal to the MAC and per-packet overrides, the MAC may pad the frame and/or append a valid FCS. In half-duplex mode, the MAC adheres to the carrier sense multiple access/collision detect access method. In full-duplex mode, the MAC ignores ignore carrier and collisions. Following each packet transmission or abortion, a transmit statistics vector is output for external statistics collection.

The external PHY presents receive packets to the MAC; the MAC then scans the preamble looking for the start frame delimiter. When found, the preamble and start frame delimiter are stripped and the frame is passed to the system; following each frame reception, a receive statistics vector is outputted for frame filtering and statistics collection. The MAC also outputs nine bits of the cyclic redundancy check (CRC) sequence of the destination address for hash table lookup and filtering common in many network interface card (NIC) applications.

The PE-MCXMAC also contains the MAC control sub-layer, which adheres to IEEE 802.3x Clause 31 and Annexes 31A and 31B. Clause 31 defines MAC control frames distinguishable by their unique length-and-type field identifier (88-08) and introduces the optional MAC control sub-layer to the popular layer stack, allowing for real-time MAC operation control and manipulation. The MAC also supports both symmetric and asymmetric flow control. Presently, only pause control frames are defined; other control frames can be supported via optional configuration bits.

The MIIM communicates between the host processor and an external MII physical device by means of a two-wire interface (MDIO). The host block provides a central repository for register logic and a 32-bit processor independent control and configuration interface for the PE-MCXMAC.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Target
Device
Speed
Grade
Utilization Performance
(fMAX)
(2)
Parameter Setting
LEs (1) ESBs (2) None
Stratix® -5 2,355 0  - 125 MHz Contact Mentor Graphics

Notes to Table 1:

  1. LE = Logic element
  2. ESB = Embedded system block

Deliverables

Encrypted electronic design interface format (EDIF) netlist:

  • Quartus® II software constraint files
  • Design documentation
  • Verilog functional testbench

Contact Information

For additional information, contact:

Mentor Graphics
1001 Ridder Park Dr.
San Jose, CA 95131
Tel. (509) 465-3523
Fax (408) 487-7380
Email: mentor_ip@mentor.com (Netlist Sales)
URL: www.mentor.com/products/ip/index.cfm

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