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As the leading provider of 10 Gbps Ethernet (GbE) in 40-nm FPGAs, Altera offers the 10GBASE-R PHY MegaCore® function intellectual property (IP) core for designers to easily build systems with very high throughput-rate Ethernet connection using the fewest number of I/O pins. This 10GBASE-R PHY along with a 10GbE media access control (MAC) IP core enables an Altera® device to interface to a 10GbE network through a variety of external devices, including 10GbE PHY device or optical transceiver module.
You can implement the 10GBASE-R PHY in Altera devices with serial transceivers faster than 10 Gbps. The physical coding sublayer (PCS) part of this PHY is implemented in soft IP in Altera's Stratix® IV GT FPGAs and Stratix V FPGAs with serial transceivers and in integrated hard silicon IP in Stratix V FPGAs with serial transceivers. The PHY management functions are implemented in soft IP. Figure 1 illustrates an example of 10GBASE-R PHY in Altera devices.
Figure 1. 10GBASE-R PHY in an Altera Device
Note:
- 10GBASE-R PCS is in soft IP in Stratix IV GT devices, but in hard integrated IP in Stratix V GX and GT FPGAs
- SDR XGMII = single data rate XGMII, 72 bits @156.25 Mbps
- Some SFI system channels may need EDC chip here
Rich Features
- Complete 10 GbE 10GBASE-R PHY solution for 10.3125-Gbps serial external connection to XFI and SFI interfaces or XFP and SFP+ modules
- PHY consisting of 10GBASE-R PCS and 10.3125-Gbps physical medium attachment (PMA), and PHY management functions
- Direct interface with Altera® 10GbE MAC for a complete single-chip solution
- PHY integrated into hard silicon in Stratix V FPGAs with serial transceivers; also soft 10GBASE-R PCS available in Stratix IV GT and Stratix V FPGAs with serial transceivers
- Direct 10.3125-Gbps serial connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, and backplane applications
- Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various 10GBASE-R channel characteristics and devices in systems during operation
- Implementing the Ethernet standard 10GBASE-R PHY functions: 64b/66b encoding/decoding, scrambling/descrambling, receiver rate matching for clock frequency compensation, 66b/16b gear-boxing, and data serialization/deserialization to and from 10.3125-Gbps line
- Receiver-link fault status detection
- Local serial loop-back from transmitter to receiver at serial transceiver for testing
- High-performance internal system interfaces
- Altera Avalon®-Streaming (Avalon-ST) single data rate (SDR) XGMII, 72 bits @156.25 Mbps for data transfer
- Altera Avalon Memory-Mapped (Avalon-MM) 32 bits for slave management
Easy to Use
- Complete 10GbE 10GBASE-R PHY solution available to start your design quickly
- IP functional simulation models for Verilog HDL simulators; VHDL simulation models and Stratix V FPGA serial transceiver simulation models available in a future release
- 10GbE MAC + 10GBASE-R PHY verification testbench and design example
- Development boards
- Configuration and generation by the Altera MegaWizardTM Plug-in Manager GUI and SOPC Builder software
- Easy system integration with Altera SOPC Builder software
Robust Solution
- IEEE 802.3 10GbE standard compliant, clauses 46, 49, and 51
- Extensively validated in simulation and in hardware with standard 10GbE tester
Protocol Solution
- Detailed documentation on how to use the IP core
- Step-by-step instructions to get started
- Altera devices with 10GBASE-R PHY feature
- Complete description of Altera device capabilities
- Design example for quick and easy design start
- Other related IP and solutions
Performance
Typical expected performance and resource utilization figures for this IP core are provided in the 10GBASE-R PHY Resource Utilization and Performance (PDF).
Technical Support
For technical support on this IP core, please visit Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Solutions Database.
