XAUI PHY MegaCore Function

from Altera

As the leading provider of 10-Gbps Ethernet (GbE) 40-nm FPGAs, Altera offers the XAUI PHY MegaCore^® function intellectual property (IP) core for you to easily build systems with very high throughput-rate Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera^® device to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module.

You can implement the XAUI PHY (excluding the PHY management functions) in hard silicon in Altera FPGAs with serial transceivers faster than 3 Gbps . The PHY management functions are implemented in soft IP. XAUI PHY can also be implemented in soft IP form in Stratix^® IV and Stratix V FPGAs with serial transceivers. Additionally, for applications requiring 20-Gbps throughput, Altera's XAUI PHY solution can support DXAUI (4x 6.25 Gbps) implementations on Stratix IV (GX and GT) FPGAs. Figure 1 illustrates an example of XAUI PHY in Altera devices.

Figure 1. XAUI PHY in an Altera Device

Note:

1. XAUI PCS is in hard integrated IP in Altera devices with serial transceivers, and it can also be in soft IP in Stratix IV GX, Stratix IV GT, and Stratix V GX, GT, and GS FPGAs
2. SDR XGMII = single data rate XGMII, 72 bits at 156.25 Mbps

Rich Features

• Complete 10G Ethernet (XAUI) PHY solution for 4 x 3.125-Gbps serial external interface
• PHY consisting of 10GBASE-X physical coding sublayer (PCS), physical medium attachment (PMA), XGMII Extender Sublayer (XGXS), 10G Ethernet (XAUI), and PHY management functions
• Direct interface with Altera's 10GbE MAC for a complete solution
• Direct standard XAUI PHY (4 x 3.125-Gbps) connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, backplane, and short cable applications
• PHY integrated into hard silicon in Altera devices with serial transceivers above 3 Gbps; also soft XAUI PCS available in Stratix IV and Stratix V FPGAs with serial transceivers
• Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various XAUI channel characteristics and devices in systems during operation
• Implementing the Ethernet-standard XAUI PHY functions: data and control bits 8b/10b encoding/decoding and per-lane synchronization, data serialization/deserialization (SERDES) to and from 4 x 3.125-Gbps line, receiver four-data lane alignment, deskew, and alignment of four lanes, and receiver rate matching for clock frequency compensation
• Local serial loopback from transmitter to receiver at the device's serial transceiver for self testing
• High-performance internal system interfaces
  • Altera Avalon^®-Streaming (Avalon-ST) SDR XGMII, 72 bit at 156.25 Mbps for data transfer
  • Altera Avalon Memory-Mapped (Avalon-MM) 32 bit for slave management
• DXAUI (4 x 6.25-Gbps) support for Stratix IV (GX and GT) FPGAs

Easy to Use

• Complete 10G Ethernet (XAUI) PHY solution available to start your design quickly
  • IP functional simulation models for Verilog HDL simulators
    • VHDL support and Stratix V FPGA serial transceiver simulation models available in a future release
  • Verification testbench and design example
  • Development boards
• Configuration and generation by Altera MegaWizard^TM Plug-in Manager GUI and SOPC Builder software

Robust Solution

• IEEE 802.3 10GbE standard-compliant, clauses 46, 47, and 48
• Extensively validated in simulation and in hardware with standard 10GbE tester

Protocol Solution

• Detailed documentation on how to use the IP core
  • XAUI PHY User Guide (PDF)
• Step-by-step instructions to get started
• Complete description of Altera device capabilities
  • Stratix V FPGA
  • Stratix IV FPGA
  • Arria^® II FPGA
  • Cyclone^® IV GX FPGA
• Design example for quick and easy design start
• Altera 10GbE MAC
• For other 10GbE solutions see Altera Wireline Solutions

Performance

Typical expected performance and resource utilization figures for this IP core are provided in the XAUI PHY Resource Utilization and Performance (PDF).

Technical Support

For technical support on this IP core, please visit Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Solutions Database. For IP release notes of this and other Altera IP cores please see MegaCore IP Library Release Notes and Errata.