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As the leading provider of 10-Gbps Ethernet (GbE) in 40-nm FPGAs, Altera offers the 10GbE MegaCore® function intellectual property (IP) core for easily building systems with very high throughput-rate Ethernet connection. This 10GbE media access control (MAC) along with a XAUI PHY IP core or 10GBASE-R PHY IP core enables an Altera® device to interface to an external 10GbE PHY device or optical transceiver module and, in turn, to a 10GbE network.
You can implement the XAUI PHY in hard silicon in Altera FPGAs with gigabit serial transceivers. Stratix® IV GT and Stratix V GX and GT FPGAs support 10G serial transceivers (10GBASE-R) to interface to XFI or SFP+ modules. You can implement the complete 10GBASE-R PHY in hard silicon in Stratix V GX and GT FPGAs. Figures 1, 2, and 3 illustrate examples of Altera 10GbE MAC in different Altera devices with XAUI, XFI/SFI, or XGMII interfaces, respectively.
Figure 1. 10GbE MAC in an Altera Device with XAUI Interface
Note:
- SDR XGMII = Single data rate (SDR) XGMII (72 bits at 156.25 Mbps)
- XAUI physical coding sublayer (PCS) is in hard integrated IP in all Altera devices with serial transceivers, and it can also be in soft IP in Stratix IV GX and Stratix IV GT FPGAs
- Avalon®-Streaming (ST) single-clock FIFO use is optional
- Avalon-Memory Mapped (MM) bridge is an SOPC Builder component
Figure 2. 10GbE MAC in an Altera Device with XFI or SFI 10G Serial Transceiver
Note:
- Some 10.3-Gbps SFI system channels may need EDC chip here
- 10GBASE-R PCS is in soft IP in Stratix IV GT FPGA, but is in hard integrated IP in Stratix V GX and Stratix V GT FPGAs
- Avalon-ST single-clock FIFO use is optional
- I2C Controller IP can be licensed from Altera IP partners
Figure 3. 10GbE MAC in an Altera device with XGMII Parallel Interface
Note:
- SDR XGMII = Single Data Rate XGMII (72 bits at 156.25 Mbps)
- Avalon-ST single-clock FIFO use is optional
Rich Features
- 10GbE MAC IP
- Interfaces directly to external devices or optical modules with Altera's integrated standard XAUI PHY (4 x 3.125 Gbps), 10GBASE-R PHY (10.3125 Gbps), or XGMII (32 x 312.5 Mbps)
- Deficit idle count (DIC)
- Local and remote fault signaling
- Automatic Ethernet flow control
- Programmable maximum receiving frame length up to 16 KB including jumbo frames
- Promiscuous (transparent) and non-promiscuous (filtered) operation modes
- Programmable MAC addresses and receive packet filtering based on MAC addresses
- Programmable received frame filtering with cyclical redundancy check (CRC), length check, or oversized frame error
- Support for virtual LAN (VLAN) and stacked VLAN tagged frames according to the IEEE 802.1Q and 802.1ad (Q-in-Q) standards, respectively
- Statistics counters for RMON (RFC 2819), Ethernet-type MIB (RFC 3635), and interface group MIB (RFC 2863)
- High-performance internal system interfaces
- Altera Avalon-Streaming (Avalon-ST) 64 bit @156.25 Mbps for data transfer to and from user application logic
- Altera Avalon Memory-Mapped (Avalon-MM) 32 bit for slave management
- Altera Avalon-Streaming (Avalon-ST) SDR XGMII, 72 bit @156.25 Mbps for data transfer to and from PHY IP core
- Complete design examples
- 10GbE MAC and various PHYs
- Parameterizable FIFO with store-and-forward or pass-through modes, and drop-on-bad frame
- Remote (line) and local (client) loopback at XGMII for system test
- Management data I/O (MDIO) master IP core
- 10GbE Hardware Demonstration Reference Design with support for dual XAUI to SFP+ HSMC Board from Terasic
Ease of Use
-
Complete 10GbE protocol solution available in design examples to start your design quickly
- IP functional simulation models for Verilog HDL and VHDL simulators
- Some 10GbE PHY IP core simulation models available in a future release.
- IP functional simulation models for Verilog HDL and VHDL simulators
- Verification testbench and hardware design examples
- Development boards
- Configuration and generation by Altera MegaWizardTM Plug-in Manager GUI and SOPC Builder software
- Easy system integration with SOPC Builder software
Robust Solution
- IEEE 802.3 10GbE MAC standard compliant, clauses 4, 31, and 46
- Extensively validated in simulation and in hardware with standard 10GbE tester
Protocol Solution
- Detailed documentation on how to use the IP core
- Step-by-step instructions to get started
- Complete description of Altera device capabilities supporting this IP core
- Design example for quick and easy design start
- PHY IP cores for 10GbE MAC
- For other 10GbE solutions see Altera Wireline Solutions
Performance
Typical expected resource utilization and performance figures for this IP core are provided in the 10-Gbps Ethernet MAC Resource Utilization and Performance (PDF).
Technical Support
For technical support on this IP core, please visit Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Solutions Database. For IP release notes of this and other Altera IP cores please see MegaCore IP Library Release Notes and Errata.
