10-Gigabit Ethernet Physical Coding Sub-layer (PCS)
Features
- 10-GBASE-R core is compliant with Clause 49 of IEEE 802.3ae specification
- Designed for 10-Gbit Ethernet physical layer (PHY) applications such as local area network/wide area network (LAN/WAN) PHYs or for use in integrated 10-Gbit Ethernet controller devices
- Optional features include 64-bit, media-independent non-double data rate (DDR) interface; 32-bit XGMII (10-Gbit medium independent interface) DDR-to-10-Gbit Ethernet media access controls (MACs); and high-speed serializer/deserializer (SERDES)
- Optional 10-Gbit attachment unit interface (XAUI) can be implemented with transceivers for efficient, board-level interface to optical modules and loopback
- Optional XAUI interface is compatible with the Xenpack version 2.0 specification
- Implements 4-to-1, 10-Gbit 16-bit interface (XSBI) multiplexer/de-multiplexer when selected technology is an Altera® FPGA
- Implements 10-Gbit Ethernet data scrambler that generates transition-rich signals to an application's high-speed optical link and its data descrambler on the core receive path
- Available for Altera's Stratix™ and Stratix GX FPGAs
- Includes 64- and 66-bit data coder/decoder (CODEC), with synchronization bit insertion or deletion upon respective transmit or receive
- Provides 66-bit block synchronization on the physical coding sub-layer receive path, and 64-bit block encoding on transmit with gearbox function
- Includes 64- and 66-bit encoder/decoder that performs 66-bit word alignment; 64- and 66-bit receive path decoding; 64- and 66-bit transmit path encoding; and 64- and 66-bit transmit path conversion for block overhead bits
- Implements XGMII and XSBI clock rates decoupling with elastic buffers on the transmit and receive paths
- Simplifies system clock distribution through rate-matching first-in first-out (FIFO) with idle insertion or removal in receive direction
- Provides programmable loopback on the core XGMII interface available for application test
- Implements test pattern generator and checker for link testing in accordance with Clauses 49.2.8 and 49.2.12 of IEEE 802.3ae
- Implements bit error rate monitoring, with high error rate indication to ensure constant line quality monitoring
- Connects seamlessly to the MorethanIP 10-Gbit Ethernet MAC to function as a single-chip 10-Gbit Ethernet controller
- Optional Management Data Interface (xMDIO) provides access to the internal registers of the PCS according to Clause 45 (definition of extended MDIO) of IEEE 802.3ae
- Includes complete design kit containing behavioral Ethernet frame generators and checking models, PCS traffic generation model, standard compliance scenario, and implementation scripts
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. 10 Gigabit Ethernet Physical Coding Sub-layer (PCS) Block Diagram 
Description
The MorethanIP PCS (Physical Coding Sub-layer) core is designed for Ethernet LAN PHY implementations, and can be used in Xenpack module applications or, when combined with proven MorethanIP 10-Gbit MACs, in highly integrated 10-Gbit Ethernet controller solutions. The MorethanIP PCS core is available for Altera Stratix, Stratix GX, and Mercury™ FPGAs.
The 10GBASE-R PCS core includes several functions, including a line scrambler-descrambler, 64- and 66-bit encoder and decoder, block synchronization, bit error testing, loopback, and test pattern generation and checking.
On the application side, the PCS core can be configured to implement either a XGMII or a XAUI when a design targets Altera Stratix GX FPGAs. Users can select the XGMII interface when integrating the core and custom logic into an FPGA solution. Alternatively, the XAUI interface provides a simple 16-bit, board level interface to connect the core to a MAC device.
The core is for use within LAN/WAN applications, with the PCS attached directly to the transceiver module; optional features include the test pattern generator and checker.
The 10GBASE-R PCS core is IEEE 802.3ae-compliant.
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Target Device |
Speed Grade |
Utilization
Logic Cells |
Performance
(fMAX) |
Parameter Setting |
| EP1S20 |
-6 |
6,900 |
185 MHz |
161.3 MHz |
| EP1SGX25 |
-6 |
7,020 |
185 MHz |
161.3 MHz |
Deliverables
- Register transfer level (RTL) synthesizable VHDL/Verilog source code or encrypted netlist
- Configurable VHDL/Verilog verification testbenches
- Scripts for Mentor Graphics® LeonardoSpectrum™ synthesis tool
- Implementation script for the Quartus® II software version 2.1
- Detailed user guides
Contact InformationFor additional information, you can contact MorethanIP at:
MorethanIP
An der Steinernen Bruecke 1
D-85757
Karlsfeld Germany
Tel: +49 81-31-333-9390 (Germany) or +1 408 273 4567 (USA)
Fax: +49 81-31-333-9391 (Germany) or +1 408 273 4667 (USA)
E-mail: info@morethanip.com
Internet: http://www.morethanip.com
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