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10/100/1000 1588 Ethernet MAC Core

from MorethanIP

View Literature
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AMPP Approved
OpenCore Support



Features

  • Media access control (MAC) functions      
    • UNH certified
    • Preamble and start-of-frame delimiter (SFD) insertion and deletion
    • Optional padding termination/insertion for NIC applications or forwarding of unmodified frames for switching applications
    • Support for virtual local area network (VLAN)-tagged frames according to IEEE 802.1Q specification in both transmit and receive functions
    • CRC-32 checking at full speed using a multi-stage, cyclic redundancy code
      (CRC) calculation architecture with optional forwarding of the frame check sequence (FCS) field to the user application
    • CRC-32 generation and append on transmit or forwarding of user application provided FCS selectable on a per-frame basis
    • Per channel individual unicast MAC address for frame filtering or fully transparent operation
    • Programmable frame length to support standard and proprietary frame lengths
    • Embedded programmable multicast address resolution hash table
    • Programmable half duplex out, full duplex network operation (10/100 Mbps)
    • Half duplex collision and automatic frame re-transmission with jamming and back-off timer
    • Optional automatic pause frame generation from programmable first-in first-out (FIFO) congestion thresholds or by dedicated command pin with programmable Quanta
    • Per channel programmable automatic Xon and Xoff flow control frame generations
    • Network statistics
  • IEEE 1588 support
    • Support for all IEEE 1588 frames
    • Reference clock can be chosen independently of the network speed
    • Software programmable precise time stamping of ingress frames and egress frames
    • Timer monitoring capabilities for system calibration and timing accuracy management
    • Precise time stamping of external events with programmable interrupt generation
    • Programmable event and interrupt generation for external system control
    • Hardware and software controllable timer synchronization
  • Development boards
    • Standard Altera® Cyclone® II, Stratix®, and Stratix II FPGA prototyping and development boards
    • Comprehensive 10/100 and 10/100/1000 Ethernet PHY board selection

Block Diagram

Figure 1 Shows the 10/100/1000 1588 Ethernet MAC core.

Figure 1. 10/100/1000 1588 Ethernet MAC Core

Figure 1. Tri-Speed 1588 Ethernet MAC Core

Adobe Acrobat IconClick for full detail

Description

For industrial automation applications, the IEEE 1588 standard is becoming the main technology for precise time synchronization on Ethernet networks, providing accurate clock synchronization for distributed control nodes (overcomes one of the drawbacks of Ethernet networks).

The programmable 10/100/1000 Ethernet MAC along with IEEE 1588 integrates a standard IEEE 802.3 Ethernet MAC with a time-stamping module to support Ethernet applications. This requires precise timing references for incoming and outgoing frames to implement a distributed time synchronization protocol.

You can integrate the 10/100/1000 1588 MAC core in multiple applications from line card to switches and provides a 2.5-ns precision for frame stamping, event generation, or event capture. This megafunction is a fully validated IEEE 1588 MAC intellectual property (IP) core implemented on Altera Stratix II and Cyclone II devices.

A dual PCI 1588 controller (and associated Windows or Linux networking drivers) is available, and can be used for rapid prototyping and deployment in standard PC or processor environments.

Device Utilization and Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction

Target Altera Device

Speed Grade

Logic Elements (LEs)

Performance
(fMAX)
Parameter Setting

Stratix II

-5 3,700 to 5,500 180 MHz 125 MHz

Cyclone II

-8 4,000 to 6,000

135 MHz

125 MHz

Deliverables

  • Register transfer level (RTL) synthesizable VHDL/Verilog HDL source code or encrypted code
  • Configurable VHDL/Verilog HDL verification testbenches
  • Implementation script for Quartus® II design software
  • Detailed user and reference guide

Contact Information

For additional information, contact MorethanIP at:

MorethanIP
Muencher Strasse 199
D-85757
Karlsfeld Germany

Tel: +49 81-31-333-9390
Fax: +49 81-31-333-9391
Email: info@morethanip.com
WWW: www.morethanip.com

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