AnySpeed Ethernet MAC
Features
- Full media access control (MAC) layer and reconciliation sub-layer implementation compliant with IEEE 802.3ae and IEEE 802.3z specifications
- Dynamically configurable to support 10-Gigabit Ethernet with XGMII interface or Gigabit Ethernet with GMII interface applications
- Can be configured for NIC applications or switching/bridging applications
- Lane, data alignment, PHY error, and local/remote fault signaling handled by the core's reconciliation sub-layer
- CRC-32 checksum at full speed using a multistage cyclic redundancy check (CRC) calculation architecture with optional forwarding of the FCS field to the user application
- Optional MAC address comparison on receive and overwrite on transmit for NIC applications
- Selectable promiscuous frame receive mode and transparent MAC address forwarding on transmit
- Optional multicast address filtering with 64-bin hash code look-up table (LUT) on receive reducing processing load on higher layers
- Optional Ethernet pause frame (802.3 Annex 31A) termination providing fully automated flow control without any user application overhead
- Optional automatic pause frame generation from programmable FIFO congestion thresholds or by dedicated command pin with programmable quanta
- Programmable frame maximum length providing support for any frame (e.g., jumbo frame or any tagged frame)
- Support for VLAN tagged frames according to IEEE 802.1Q specification in both transmit and receive
- Dynamic packet gap (IPG) calculation for WAN applications
- Deficit idle counter (DIC) for optimized performance with minimum IPG for LAN applications
- Clock and data rate decoupling with programmable asynchronous FIFO buffers
- 64-bit user application interface compatible with Altera® Atlantic® SOC (system-on-a-chip) interface
- Optional 802.3 basic and mandatory managed objects statistic counters and IETF Management Information Database (MIB) package (RFC2665) and Remote Network Monitoring (RMON) counters
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. AnySpeed Ethernet MAC Block Diagram
Description
The programmable AnySPEED Ethernet MAC from MorethanIP provides, with a single IP core, a solution for Ethernet applications (line card, NIC card, or switching) operating at 10/100/1000 Mbps (Gigabit Ethernet) or 10,000 Mbps (10 Gigabit). The AnySPEED MAC Core operates in full duplex mode, supports transparent (for switching applications) and Ethernet frame termination/generation (for NIC or line card applications) with padding and wire speed CRC check/generation.
The core can seamlessly connect to any industry-standard Ethernet PHY devices via a Gigabit Medium Independent Interface (GMII for 1000-Mbps application), Medium Independent Interface (MII for 10/100-Mbps applications), 10-Gigabit interface, and to a user application via a 64-bit SOC interface which provides seamless connectivity to any MorethanIP cores such as Flexbus, POS-PHY L4, or third party cores, such as PCI-Express interfaces, which implement an interface compatible with the Altera Atlantic specification.
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization Results for AnySpeed Ethernet MAC |
| Target Device |
Speed Grade |
Utilization
Logic Cells |
Performance
(fMAX) |
Parameter Setting |
| Stratix® II |
-5 |
6000-7900 |
190 MHz |
Contact MorethanIP |
Deliverables
- Detailed user guide and reference guide
- Register transfer level (RTL) synthesizable VHDL/Verilog source or encrypted code
- Configurable VHDL/Verilog verification test-benches
- Implementation script for Quartus® II development software
Contact Information
For additional information, you can contact:
MorethanIP GmbH
Münchner Strasse 199
D-85757 Karlsfeld
GERMANY
Tel: +49 81-31-333-9390 (Germany) or +1 408 273 4567 (USA)
Fax: +49 81-31-333-9391 (Germany) or +1 408 273 4667 (USA)
Email: info@morethanip.com
URL: www.morethanip.com
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