Interlaken Protocol

from Altera

The Interlaken protocol is a royalty-free specification that builds on the logical structure of SPI-4.2 (System Packet Interface Level 4 interface technology) that is widely deployed in networking equipment. Jointly developed by Cortina and Cisco Systems, the Interlaken protocol is more robust than SPI-4.2, providing better error checking and data integrity. Interlaken is also a more scalable protocol; SPI-4.2 doesn't scale beyond 10G. Interlaken allows use of the latest 6G serial technology in configurable increments, allowing you to build interfaces that support 20G to 40G applications as well as next-generation systems that will run at 100G and beyond.

Compared to SPI-4.2, Interlaken generates a 90 percent reduction in pin count. That translates into lower cost on the board and lower cost on the chips. Another big advantage of Interlaken is scalability. The same interface and the same protocol can be used anywhere from 10G to 100G. Altera's Interlaken solution is an extremely flexible compiler-based product.

Interlaken uses serializer/deserializer (SERDES) technology to garner more bandwidth. The built-in SERDES blocks in our Stratix^® or Arria^® FPGA family can run at data rates up to 12.5 Gbps, which the core can handle with ease. The lanes are programmable and can scale the protocol up to a higher bandwidth through the addition of more lanes—the core function doesn't need to change. In the middle of the core is logic that sits in front and behind the SERDES channels that's replicated per lane. On the right side of the core is the protocol layer—TX striping and RX de-striping.

Depending on what bandwidth is required, the bus that faces the FPGA is between 128 to 512 bits for 10G up to 100G, respectively. There's an optional test interface that allows you to inject expected errors in the protocol and into each lane for testing of the FPGA circuitry and the other device that's connected to it. Altera's Interlaken IP solution is completely tested against other industry solutions and is scalable to support 10G line rates. In the Stratix V FPGA family the 64B/67B encoder/decoder functionality is hardened within the device.

• Interlaken Compiler Features
  • Support for up to 24 lanes
  • Supports 10G+ line rates (covers CEI-11G specifications)
  • Programmable BurstMin, BurstMax, Burst Short, and MetaFrame length
  • Multiple channel support
  • Data stripping and de-stripping of all individual lanes
  • Built-in word and lane alignment
  • CRC-24 and CRC-32 for burst and lane integrity
  • In-band and out-of-band flow control support
  • Error detection and lane diagnostics
• Key Benefits
  • Optimized for Altera^® devices and compiler format
  • Proven timing closure for complete system integration
  • Proven inter-operability at 6.25-Gbps line rate with industry ASSP solutions
• Utilization Estimates
  • 4 channel with arbiters , 16-bit calendar , full duplex

Figure 1 shows a high-level block diagram for Altera's Interlaken IP solution.

Figure 1. Altera Interlaken Block Diagram

Altera's Interlaken IP core is supported on the following device families:

• Stratix IV FPGAs
• Stratix V FPGAs
• HardCopy^® IV ASICs
• Arria II GZ FPGAs

Related Links

• Interlaken MegaCore Function User Guide (PDF)