from Digital Core Design
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Features
- Master operation
- Multi-master systems supported
- Performs arbitration and clock synchronization
- Interrupt generation
- Supports speeds up to 3.4 megabits per second (Mbps) (standard, fast, and high-speed mode)
- Allows operation from a wide range of input clock frequencies (built-in 8-bit timer)
- User-defined timing
- Fully synthesizable, static synchronous design with no internal tri-states
Block Diagram
Figure 1 shows the block diagram for the DI2CM I2C bus interface-master megafunction.
| Figure 1. DI2CM I2C Bus Interface-Master Block Diagram |
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Description
The DI2CM function provides an interface between a microprocessor and an I2C bus. The function can be programmed to operate with arbitration and clock synchronization in multi-master systems. The DI2CM function can be used in automotive audio-video systems and embedded microprocessor systems.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction | |||
| Device | Speed Grade | Utilization | Performance (fMAX) |
|---|---|---|---|
| Cyclone® III | -6 | 258 Logic Elements (LEs) | 280 MHz |
| Stratix® III | -2 | 205 ALUTs | 430 MHz |
| Stratix IV | -2 | 205 ALUTs | 430 MHz |
Contact Information
For additional information, contact DCD at:
Digital Core Design
Wroclawska 94
41-902 Bytom
Poland
Tel. +48 32 282 82 66
Fax +48 32 282 74 37
E-mail: aleads@dcd.pl
URL: http://www.dcd.com.pl
