DDR and DDR2 SDRAM Controller MegaCore Functions

from Altera Corporation

Included in the IP Base Suite—FREE with Quartus II Subscription

Features

Support for industry-standard DDR and DDR2 SDRAM devices and modules
- Including support for registered DIMMs
Flexible, robust design
- 1, 2, 4, or 8 chip-select signals
- Configurable data width including data strobe (DQS) read postamble control logic and optional non-DQS read mode for side banks (Stratix^® series FPGAs)
- Automatic or user-controlled refresh
- Data mask signals for partial write operations
- Bank management architecture, which minimizes latency
Quick and easy implementation
- IP Toolbench-generated constraint script
- Top-level example design shipped as a deliverable with the intellectual property (IP) MegaCore^® function
- IP functional simulation models used in Altera supported VHDL and Verilog HDL simulators
- Free clear-text data path for use with custom controller
SOPC Builder ready to enable system-level design

General Description

The DDR and DDR2 SDRAM controllers handle the complex aspects of using DDR and DDR2 SDRAM—initializing the memory devices, managing SDRAM banks, and keeping the devices refreshed at appropriate intervals. The controllers translate read and write requests from the local interface into all the necessary SDRAM command signals.

Whether you use the IP Toolbench in SOPC Builder or the Quartus^®II software, it generates an example design, instantiates a phase-locked loop (PLL), an example driver, and your DDR/DDR2 SDRAM Controller custom variation. The example design is a fully-functional example design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals.

You can replace the DDR/DDR2 SDRAM controller encrypted control logic in the example instance with your own custom logic, which allows you to use the Altera^® clear-text data path with your own control logic.

IP Evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive this IP core.

Performance

Typical expected performance and utilization figures for this MegaCore function are provided in the DDR and DDR2 SDRAM Controller Compiler User Guide (PDF).

I-Tested

Altera awards the I-Tested certification to MegaCore functions or Altera Megafunctions Partners Program (AMPP^SM) IP cores that have been verified in an Altera FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.

For more information, see MegaCore Verification in the DDR and DDR2 SDRAM Controller Compiler User Guide (PDF).

Technical Support

For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.