High-Performance Memory Controller II SDRAM MegaCore Function

from Altera

The new High-Performance Memory Controller II SDRAM MegaCore^® function for Quartus design software v11.0 handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM at speeds up to 800 Mhz. The function initializes the memory devices, manages SDRAM banks, translates read and write requests from the local interface into all the necessary SDRAM command signals, and performs command and data reordering.

The High-Performance Memory Controller II core is a drop-in replacement for the existing SDRAM controller, with many new enhanced features. New features include a quarter rate controller, 1-T and 2-T command timing to maintain command channel bandwidth, 50-percent higher random access efficiency with command and data reordering, power down and self-refresh support, and error correction code (ECC) with sub-word writes.

Figure 1. Memory Interface Layers

Whether you use the IP Toolbench in Qsys or Quartus^® II software, it generates an example design, an example driver, and the DDR1, DDR2, and DDR3 SDRAM controller, and instantiates a phase-locked loop (PLL). This fully functional design example can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller, and checks the read data to produce the pass and fail and test complete signals. Also included is an efficiency monitor which can determine the actual bandwidth of the memory bus based upon the data patterns being used.

Included in the IP Base Suite—FREE with Quartus II Subscription Edition software

Features

Support for industry-standard DDR, DDR2, and DDR3 SDRAM devices and modules
- Includes support for registered DIMMs
- Supports efficient bank interleaving
Look-ahead bank management
- Issue activate and precharge commands early
  - Use auto-precharge when possible
  - In-order read/writes (no re-ordering)
- Bank management architecture, which minimizes latency
- Read/write accesses with auto-precharge
  - Automatic cancellation of auto-precharge on page hits
Avalon^® Memory-Mapped interface
- Adaptor for native interface
- Avalon slave interface for access to CSR
Burst size adaptation for efficient DRAM accesses
- Built-in burst adapter
- Combines short local transactions into memory bursts
- Split long local transactions into memory bursts
Integrated low-latency quarter-rate, half-rate, and full-rate system interface
- Support an optional half-system interface speed
- Maintain the controller in the faster clock domain to reduce latency
Flexible, robust design
- 1, 2, 4, or 8 chip-select signals
- Configurable data width including DQ strobe (DQS) read postamble control logic and optional non-DQS read mode for side banks (Stratix^® series FPGAs)
- Automatic or user-controlled refresh
- Data mask signals for partial write operations
Quick and easy implementation
- IP Toolbench-generated constraint script
- Top-level example design shipped as a deliverable with the intellectual property (IP) MegaCore function
- IP functional simulation models used in Altera^® supported VHDL and Verilog HDL simulators
- Available in clear-text for use with custom controller
Integrated command and data reordering to allow for improved memory bandwidth efficiency
Power down and self-refresh support
Well documented clear text RTL for ease of use
Qsys Compliant to enable system-level design

IP Evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive this IP core.

Performance

Supports up to 800-MHz memory speed at quarter-rate (200-MHz controller clock)
5-cycle controller latency

Typical expected performance and utilization figures for this MegaCore function are provided in the High-Performance Memory Controller II SDRAM Controller Compiler User Guide (PDF) .

Technical Support

For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.

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