DDR and DDR2 SDRAM High-Performance Controller MegaCore Functions

from Altera

Included in the IP Base Suite—FREE with Quartus^® II Subscription Edition software

Features

• Flexible architecture
  • Supports Industry-standard DDR/DDR2 SDRAM devices and modules
  • Creates a complete DDR/DDR2 solution by bolting onto the ALTMEMPHY physical interface megafunction
• Feature rich
  • Provides full-rate application logic interface
  • Has integrated error correction coding (ECC) functionality
  • Offers optional user-controller refresh
  • Supports auto-precharge
  • Supports self-refresh and power-down modes
• Ease of use
  • Supports SOPC Builder
  • Offers optional Avalon^® Memory-Mapped local interface
  • Includes MegaWizard^® Plug-In Manager interface
  • Provides support for OpenCore Plus evaluation

General description

The Altera^® DDR and DDR2 SDRAM High-Performance Controller MegaCore^® functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM. The MegaCore functions work in conjunction with the Altera ALTMEMPHY physical interface megafunction. The controllers offer a half-rate interface and a full-rate interface to the customer application logic. For exact device support, please refer to the user guide.

The MegaWizard Plug-In Manager generates an example design, instantiates a phase-locked loop (PLL), an example driver, your DDR or DDR2 SDRAM controller custom variation, and an optional DLL (for Stratix^® series FPGAs only). The example design is a fully functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals. Figure 1 shows a system-level diagram including the example design that the DDR or DDR2 SDRAM Controller MegaCore functions create for you.

Figure 1. DDR2 SDRAM High-Performance Controller System-Level Diagram

IP evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive this MegaCore function.

Performance

Typical expected performance and utilization figures for this MegaCore function are provided in the DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide (PDF).

I-Tested

Altera awards the I-Tested certification to MegaCore functions or Altera Megafunction Partners Program (AMPP^SM) IP cores that have been verified in an Altera FPGA, on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.

Technical support

For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.

Related documents

• DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide (PDF)
• MegaCore IP Library Release Notes and Errata (PDF)