DDR3 SDRAM High-Performance Controller MegaCore Functions
from Altera Corporation
Included in the IP Base Suite—FREE with Quartus® II Design Software Subscription
Features
- Flexible architecture
- Industry-standard DDR3 SDRAM device and module support
- Ability to bolt onto the ALTMEMPHY physical interface megafunction for a complete DDR3 solution
- Feature rich
- Optional user-controlled refresh support
- Power-up calibrated on-chip termination (OCT)
- Integrate error correction coding (ECC) functionality
- Ease of use
- SOPC Builder support
- Optional Avalon® Memory-Mapped local interface
- OpenCore Plus evaluation support
- Includes MegaWizard® interface
- Intellectual property (IP) functional simulation modules for use in Altera-supported VHDL and Verilog HDL simulators
General Description
The Altera® DDR3 SDRAM High-Performance Controller MegaCore® functions provide simplified interfaces to industry-standard DDR3 SDRAM devices and modules. The MegaCore functions work in conjunction with the Altera ALTMEMPHY physical interface megafunction. These DDR3 SDRAM MegaCore functions offer a half-rate interface to the customer application logic.
Easy to Get Started
The MegaWizard Plug-In Manager generates an example design that instantiates an example driver and your DDR3 SDRAM high-performance controller custom variation. The example design is a fully functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals.
IP Evaluation
Use the Altera OpenCore Plus Evaluation flow to test drive this MegaCore function.
Performance
Typical expected performance and utilization figures for MegaCore functions are provided in the DDR3 SDRAM High-Performance Controller User Guide (PDF).
I-Tested
Altera awards the I-Tested certification to MegaCore functions or Altera Megafunctions Partners Program (AMPPSM) IP cores that have been verified in an Altera FPGA on an evaluation board, with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.
Technical Support
For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.
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